mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
31d8267224
Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
645 lines
18 KiB
C
645 lines
18 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_QE 1 /* Has QE */
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#define CONFIG_MPC83XX 1 /* MPC83XX family */
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#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
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#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
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#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
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#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
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/*
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* System Clock Setup
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*/
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#ifdef CONFIG_PCISLAVE
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#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
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#else
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#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 66000000
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#endif
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/*
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* Hardware Reset Configuration Word
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*/
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#define CFG_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_1X1 |\
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HRCWL_CSB_TO_CLKIN_4X1 |\
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HRCWL_VCO_1X2 |\
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HRCWL_CE_PLL_VCO_DIV_4 |\
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HRCWL_CE_PLL_DIV_1X1 |\
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HRCWL_CE_TO_PLL_1X6 |\
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HRCWL_CORE_TO_CSB_2X1)
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#ifdef CONFIG_PCISLAVE
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_AGENT |\
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HRCWH_PCI1_ARBITER_DISABLE |\
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HRCWH_PCICKDRV_DISABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0XFFF00100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT)
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#else
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_PCICKDRV_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT)
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#endif
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/*
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* System IO Config
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*/
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#define CFG_SICRH 0x00000000
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#define CFG_SICRL 0x40000000
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* IMMR new address
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*/
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#define CFG_IMMR 0xE0000000
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/*
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* DDR Setup
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*/
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CFG_83XX_DDR_USES_CS0
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#define CONFIG_DDR_ECC /* support DDR ECC function */
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#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
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/*
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* DDRCDR - DDR Control Driver Register
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*/
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#define CFG_DDRCDR_VALUE 0x80080001
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#if defined(CONFIG_SPD_EEPROM)
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/*
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* Determine DDR configuration from I2C interface.
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*/
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#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
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#else
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/*
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* Manually set up DDR parameters
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*/
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#define CFG_DDR_SIZE 256 /* MB */
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#if defined(CONFIG_DDR_II)
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#define CFG_DDRCDR 0x80080001
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#define CFG_DDR_CS0_BNDS 0x0000000f
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#define CFG_DDR_CS0_CONFIG 0x80330102
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#define CFG_DDR_TIMING_0 0x00220802
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#define CFG_DDR_TIMING_1 0x38357322
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#define CFG_DDR_TIMING_2 0x2f9048c8
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#define CFG_DDR_TIMING_3 0x00000000
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#define CFG_DDR_CLK_CNTL 0x02000000
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#define CFG_DDR_MODE 0x47d00432
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#define CFG_DDR_MODE2 0x8000c000
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#define CFG_DDR_INTERVAL 0x03cf0080
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#define CFG_DDR_SDRAM_CFG 0x43000000
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#define CFG_DDR_SDRAM_CFG2 0x00401000
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#else
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#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
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#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
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#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
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#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
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#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
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#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
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#endif
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#endif
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/*
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* Memory test
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*/
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00000000 /* memtest region */
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#define CFG_MEMTEST_END 0x00100000
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/*
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* The reserved memory
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*/
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
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#define CFG_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
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#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CFG_FLASH_CHECKSUM
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/*
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* BCSR on the Local Bus
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*/
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#define CFG_BCSR 0xF8000000
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#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
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#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
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#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
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#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
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/*
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* SDRAM on the Local Bus
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*/
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#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
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#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
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#ifdef CFG_LB_SDRAM
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#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
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#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
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/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
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/*
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* Base Register 2 and Option Register 2 configure SDRAM.
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* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
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*
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* For BR2, need:
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* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
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* port size = 32-bits = BR2[19:20] = 11
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* no parity checking = BR2[21:22] = 00
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* SDRAM for MSEL = BR2[24:26] = 011
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* Valid = BR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
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*
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* CFG_LBC_SDRAM_BASE should be masked and OR'ed into
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* the top 17 bits of BR2.
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*/
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#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
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/*
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* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
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*
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* For OR2, need:
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* 64MB mask for AM, OR2[0:7] = 1111 1100
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* XAM, OR2[17:18] = 11
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* 9 columns OR2[19-21] = 010
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* 13 rows OR2[23-25] = 100
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* EAD set for extra time OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
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*/
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#define CFG_OR2_PRELIM 0xfc006901
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#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
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#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
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/*
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* LSDMR masks
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*/
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#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
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#define CFG_LBC_LSDMR_COMMON 0x0063b723
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/*
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* SDRAM Controller configuration sequence.
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*/
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#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
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| CFG_LBC_LSDMR_OP_PCHALL)
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#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
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| CFG_LBC_LSDMR_OP_ARFRSH)
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#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
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| CFG_LBC_LSDMR_OP_ARFRSH)
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#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
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| CFG_LBC_LSDMR_OP_MRW)
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#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
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| CFG_LBC_LSDMR_OP_NORMAL)
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#endif
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/*
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* Windows to access PIB via local bus
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*/
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#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
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#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
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/*
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* CS4 on Local Bus, to PIB
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*/
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#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
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#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
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/*
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* CS5 on Local Bus, to PIB
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*/
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#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
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#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
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#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_FSL_I2C
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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#define CFG_I2C2_OFFSET 0x3100
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CFG_PCI_MEM_BASE 0x80000000
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
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#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_MMIO_BASE 0x90000000
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#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
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#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_IO_BASE 0x00000000
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#define CFG_PCI_IO_PHYS 0xE0300000
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#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
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#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
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#define CFG_PCI_SLV_MEM_BUS 0x00000000
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#define CFG_PCI_SLV_MEM_SIZE 0x80000000
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#ifdef CONFIG_PCI
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_UEC_ETH
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#define CONFIG_ETHPRIME "FSL UEC0"
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#define CONFIG_PHY_MODE_NEED_CHANGE
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#define CONFIG_UEC_ETH1 /* GETH1 */
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#ifdef CONFIG_UEC_ETH1
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#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
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#define CFG_UEC1_RX_CLK QE_CLK_NONE
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#define CFG_UEC1_TX_CLK QE_CLK9
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#define CFG_UEC1_ETH_TYPE GIGA_ETH
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#define CFG_UEC1_PHY_ADDR 0
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#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
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#endif
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#define CONFIG_UEC_ETH2 /* GETH2 */
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#ifdef CONFIG_UEC_ETH2
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#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
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#define CFG_UEC2_RX_CLK QE_CLK_NONE
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#define CFG_UEC2_TX_CLK QE_CLK4
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#define CFG_UEC2_ETH_TYPE GIGA_ETH
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#define CFG_UEC2_PHY_ADDR 1
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#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
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#endif
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/*
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* Environment
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*/
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#ifndef CFG_RAMBOOT
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
|
#define CFG_ENV_SECT_SIZE 0x20000
|
|
#define CFG_ENV_SIZE 0x2000
|
|
#else
|
|
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
|
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
|
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
|
#define CFG_ENV_SIZE 0x2000
|
|
#endif
|
|
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
|
|
/*
|
|
* BOOTP options
|
|
*/
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
#define CONFIG_BOOTP_BOOTPATH
|
|
#define CONFIG_BOOTP_GATEWAY
|
|
#define CONFIG_BOOTP_HOSTNAME
|
|
|
|
|
|
/*
|
|
* Command line configuration.
|
|
*/
|
|
#include <config_cmd_default.h>
|
|
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_I2C
|
|
#define CONFIG_CMD_ASKENV
|
|
#define CONFIG_CMD_SDRAM
|
|
|
|
#if defined(CONFIG_PCI)
|
|
#define CONFIG_CMD_PCI
|
|
#endif
|
|
|
|
#if defined(CFG_RAMBOOT)
|
|
#undef CONFIG_CMD_ENV
|
|
#undef CONFIG_CMD_LOADS
|
|
#endif
|
|
|
|
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CFG_LONGHELP /* undef to save memory */
|
|
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
#else
|
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
|
#endif
|
|
|
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
|
#define CFG_MAXARGS 16 /* max number of command args */
|
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
|
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 8 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
|
|
/*
|
|
* Core HID Setup
|
|
*/
|
|
#define CFG_HID0_INIT 0x000000000
|
|
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
|
|
#define CFG_HID2 HID2_HBE
|
|
|
|
/*
|
|
* MMU Setup
|
|
*/
|
|
|
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
|
|
|
/* DDR: cache cacheable */
|
|
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT0L CFG_IBAT0L
|
|
#define CFG_DBAT0U CFG_IBAT0U
|
|
|
|
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
|
#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT1L CFG_IBAT1L
|
|
#define CFG_DBAT1U CFG_IBAT1U
|
|
|
|
/* BCSR: cache-inhibit and guarded */
|
|
#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT2L CFG_IBAT2L
|
|
#define CFG_DBAT2U CFG_IBAT2U
|
|
|
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
|
#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_DBAT3U CFG_IBAT3U
|
|
|
|
/* Local bus SDRAM: cacheable */
|
|
#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT4L CFG_IBAT4L
|
|
#define CFG_DBAT4U CFG_IBAT4U
|
|
|
|
/* Stack in dcache: cacheable, no memory coherence */
|
|
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
|
|
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT5L CFG_IBAT5L
|
|
#define CFG_DBAT5U CFG_IBAT5U
|
|
|
|
#ifdef CONFIG_PCI
|
|
/* PCI MEM space: cacheable */
|
|
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT6L CFG_IBAT6L
|
|
#define CFG_DBAT6U CFG_IBAT6U
|
|
/* PCI MMIO space: cache-inhibit and guarded */
|
|
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT7L CFG_IBAT7L
|
|
#define CFG_DBAT7U CFG_IBAT7U
|
|
#else
|
|
#define CFG_IBAT6L (0)
|
|
#define CFG_IBAT6U (0)
|
|
#define CFG_IBAT7L (0)
|
|
#define CFG_IBAT7U (0)
|
|
#define CFG_DBAT6L CFG_IBAT6L
|
|
#define CFG_DBAT6U CFG_IBAT6U
|
|
#define CFG_DBAT7L CFG_IBAT7L
|
|
#define CFG_DBAT7U CFG_IBAT7U
|
|
#endif
|
|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
#if defined(CONFIG_UEC_ETH)
|
|
#define CONFIG_HAS_ETH0
|
|
#define CONFIG_ETHADDR 00:04:9f:ef:01:01
|
|
#define CONFIG_HAS_ETH1
|
|
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
|
|
#endif
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
|
|
|
|
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=1000000\0" \
|
|
"ramdiskfile=ramfs.83xx\0" \
|
|
"fdtaddr=400000\0" \
|
|
"fdtfile=mpc836x_mds.dtb\0" \
|
|
""
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
|
|
|
#endif /* __CONFIG_H */
|