mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
474 lines
12 KiB
C
474 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Intel Corporation <www.intel.com>
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*/
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/misc.h>
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#include <altera.h>
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#include <common.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <watchdog.h>
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#define CFGWDTH_32 1
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#define MIN_BITSTREAM_SIZECHECK 230
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#define ENCRYPTION_OFFSET 69
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#define COMPRESSION_OFFSET 229
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#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
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#define FPGA_TIMEOUT_CNT 0x1000000
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static const struct socfpga_fpga_manager *fpga_manager_base =
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(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
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static const struct socfpga_system_manager *system_manager_base =
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(void *)SOCFPGA_SYSMGR_ADDRESS;
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static void fpgamgr_set_cd_ratio(unsigned long ratio);
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static uint32_t fpgamgr_get_msel(void)
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{
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u32 reg;
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reg = readl(&fpga_manager_base->imgcfg_stat);
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reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
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return reg;
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}
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static void fpgamgr_set_cfgwdth(int width)
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{
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if (width)
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
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ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
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else
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
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ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
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}
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int is_fpgamgr_user_mode(void)
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{
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return (readl(&fpga_manager_base->imgcfg_stat) &
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ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
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}
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static int wait_for_user_mode(void)
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{
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return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
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ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
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1, FPGA_TIMEOUT_MSEC, false);
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}
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static int is_fpgamgr_early_user_mode(void)
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{
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return (readl(&fpga_manager_base->imgcfg_stat) &
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ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
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}
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int fpgamgr_wait_early_user_mode(void)
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{
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u32 sync_data = 0xffffffff;
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u32 i = 0;
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unsigned start = get_timer(0);
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unsigned long cd_ratio;
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/* Getting existing CDRATIO */
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cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
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/* Using CDRATIO_X1 for better compatibility */
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fpgamgr_set_cd_ratio(CDRATIO_x1);
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while (!is_fpgamgr_early_user_mode()) {
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if (get_timer(start) > FPGA_TIMEOUT_MSEC)
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return -ETIMEDOUT;
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fpgamgr_program_write((const long unsigned int *)&sync_data,
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sizeof(sync_data));
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udelay(FPGA_TIMEOUT_MSEC);
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i++;
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}
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debug("Additional %i sync word needed\n", i);
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/* restoring original CDRATIO */
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fpgamgr_set_cd_ratio(cd_ratio);
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return 0;
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}
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/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
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static int wait_for_nconfig_pin_and_nstatus_pin(void)
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{
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unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
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/*
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* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
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* de-asserted, timeout at 1000ms
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*/
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return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
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true, FPGA_TIMEOUT_MSEC, false);
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}
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static int wait_for_f2s_nstatus_pin(unsigned long value)
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{
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/* Poll until f2s to specific value, timeout at 1000ms */
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return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
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ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
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value, FPGA_TIMEOUT_MSEC, false);
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}
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/* set CD ratio */
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static void fpgamgr_set_cd_ratio(unsigned long ratio)
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{
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
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(ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
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}
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/* get the MSEL value, verify we are set for FPP configuration mode */
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static int fpgamgr_verify_msel(void)
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{
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u32 msel = fpgamgr_get_msel();
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if (msel & ~BIT(0)) {
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printf("Fail: read msel=%d\n", msel);
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return -EPERM;
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}
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return 0;
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}
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/*
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* Write cdratio and cdwidth based on whether the bitstream is compressed
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* and/or encoded
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*/
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static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
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size_t rbf_size)
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{
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unsigned int cd_ratio;
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bool encrypt, compress;
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/*
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* According to the bitstream specification,
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* both encryption and compression status are
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* in location before offset 230 of the buffer.
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*/
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if (rbf_size < MIN_BITSTREAM_SIZECHECK)
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return -EINVAL;
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encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
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encrypt = encrypt != 0;
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compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
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compress = !compress;
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debug("header word %d = %08x\n", 69, rbf_data[69]);
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debug("header word %d = %08x\n", 229, rbf_data[229]);
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debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
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/*
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* from the register map description of cdratio in imgcfg_ctrl_02:
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* Normal Configuration : 32bit Passive Parallel
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* Partial Reconfiguration : 16bit Passive Parallel
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*/
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/*
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* cd ratio is dependent on cfg width and whether the bitstream
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* is encrypted and/or compressed.
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*
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* | width | encr. | compr. | cd ratio |
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* | 16 | 0 | 0 | 1 |
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* | 16 | 0 | 1 | 4 |
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* | 16 | 1 | 0 | 2 |
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* | 16 | 1 | 1 | 4 |
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* | 32 | 0 | 0 | 1 |
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* | 32 | 0 | 1 | 8 |
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* | 32 | 1 | 0 | 4 |
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* | 32 | 1 | 1 | 8 |
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*/
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if (!compress && !encrypt) {
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cd_ratio = CDRATIO_x1;
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} else {
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if (compress)
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cd_ratio = CDRATIO_x4;
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else
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cd_ratio = CDRATIO_x2;
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/* if 32 bit, double the cd ratio (so register
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field setting is incremented) */
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if (cfg_width == CFGWDTH_32)
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cd_ratio += 1;
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}
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fpgamgr_set_cfgwdth(cfg_width);
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fpgamgr_set_cd_ratio(cd_ratio);
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return 0;
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}
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static int fpgamgr_reset(void)
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{
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unsigned long reg;
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/* S2F_NCONFIG = 0 */
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
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/* Wait for f2s_nstatus == 0 */
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if (wait_for_f2s_nstatus_pin(0))
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return -ETIME;
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/* S2F_NCONFIG = 1 */
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
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/* Wait for f2s_nstatus == 1 */
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if (wait_for_f2s_nstatus_pin(1))
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return -ETIME;
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/* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
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reg = readl(&fpga_manager_base->imgcfg_stat);
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if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
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return -EPERM;
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if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
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return -EPERM;
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return 0;
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}
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/* Start the FPGA programming by initialize the FPGA Manager */
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int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
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{
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int ret;
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/* Step 1 */
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if (fpgamgr_verify_msel())
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return -EPERM;
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/* Step 2 */
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if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
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return -EPERM;
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/*
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* Step 3:
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* Make sure no other external devices are trying to interfere with
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* programming:
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*/
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if (wait_for_nconfig_pin_and_nstatus_pin())
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return -ETIME;
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/*
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* Step 4:
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* Deassert the signal drives from HPS
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*
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* S2F_NCE = 1
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* S2F_PR_REQUEST = 0
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* EN_CFG_CTRL = 0
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* EN_CFG_DATA = 0
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* S2F_NCONFIG = 1
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* S2F_NSTATUS_OE = 0
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* S2F_CONDONE_OE = 0
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*/
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
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ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
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ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
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ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
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ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
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/*
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* Step 5:
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* Enable overrides
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* S2F_NENABLE_CONFIG = 0
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* S2F_NENABLE_NCONFIG = 0
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*/
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
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ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
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/*
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* Disable driving signals that HPS doesn't need to drive.
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* S2F_NENABLE_NSTATUS = 1
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* S2F_NENABLE_CONDONE = 1
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*/
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
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/*
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* Step 6:
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* Drive chip select S2F_NCE = 0
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*/
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
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ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
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/* Step 7 */
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if (wait_for_nconfig_pin_and_nstatus_pin())
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return -ETIME;
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/* Step 8 */
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ret = fpgamgr_reset();
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if (ret)
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return ret;
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/*
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* Step 9:
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* EN_CFG_CTRL and EN_CFG_DATA = 1
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*/
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
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ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
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ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
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return 0;
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}
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/* Ensure the FPGA entering config done */
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static int fpgamgr_program_poll_cd(void)
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{
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unsigned long reg, i;
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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reg = readl(&fpga_manager_base->imgcfg_stat);
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if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
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return 0;
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if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
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printf("nstatus == 0 while waiting for condone\n");
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return -EPERM;
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}
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}
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if (i == FPGA_TIMEOUT_CNT)
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return -ETIME;
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return 0;
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}
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/* Ensure the FPGA entering user mode */
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static int fpgamgr_program_poll_usermode(void)
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{
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unsigned long reg;
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int ret = 0;
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if (fpgamgr_dclkcnt_set(0xf))
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return -ETIME;
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ret = wait_for_user_mode();
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if (ret < 0) {
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printf("%s: Failed to enter user mode with ", __func__);
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printf("error code %d\n", ret);
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return ret;
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}
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/*
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* Step 14:
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* Stop DATA path and Dclk
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* EN_CFG_CTRL and EN_CFG_DATA = 0
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*/
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
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ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
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ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
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/*
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* Step 15:
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* Disable overrides
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* S2F_NENABLE_CONFIG = 1
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* S2F_NENABLE_NCONFIG = 1
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*/
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
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ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
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/* Disable chip select S2F_NCE = 1 */
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
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ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
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/*
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* Step 16:
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* Final check
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*/
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reg = readl(&fpga_manager_base->imgcfg_stat);
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if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
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ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
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((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
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ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
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((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
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ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
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return -EPERM;
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return 0;
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}
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int fpgamgr_program_finish(void)
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{
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/* Ensure the FPGA entering config done */
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int status = fpgamgr_program_poll_cd();
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if (status) {
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printf("FPGA: Poll CD failed with error code %d\n", status);
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return -EPERM;
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}
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WATCHDOG_RESET();
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/* Ensure the FPGA entering user mode */
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status = fpgamgr_program_poll_usermode();
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if (status) {
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printf("FPGA: Poll usermode failed with error code %d\n",
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status);
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return -EPERM;
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}
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printf("Full Configuration Succeeded.\n");
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return 0;
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}
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/*
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* FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
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* Return 0 for sucess, non-zero for error.
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*/
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int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
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{
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unsigned long status;
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/* disable all signals from hps peripheral controller to fpga */
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writel(0, &system_manager_base->fpgaintf_en_global);
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/* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
|
|
socfpga_bridges_reset();
|
|
|
|
/* Initialize the FPGA Manager */
|
|
status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
|
|
if (status)
|
|
return status;
|
|
|
|
/* Write the RBF data to FPGA Manager */
|
|
fpgamgr_program_write(rbf_data, rbf_size);
|
|
|
|
return fpgamgr_program_finish();
|
|
}
|