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![Hiroyuki Yokoyama](/assets/img/avatar_default.png)
Add a USB controller driver for the EHCI block in R8A7795/R8A7796 SoC. This is a stopgap measure until we have proper DT support, clock and reset framework in place, at which point we can switch to ehci-generic. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
107 lines
2.7 KiB
C
107 lines
2.7 KiB
C
/*
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* drivers/usb/host/ehci-rcar_gen3.
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* This file is EHCI HCD (Host Controller Driver) for USB.
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*
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <usb/ehci-ci.h>
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#include "ehci.h"
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#define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000))
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#define EHCI_USBCMD 0x120
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#define CORE_SPD_RSM_TIMSET 0x30c
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#define CORE_OC_TIMSET 0x310
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/* Register offset */
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#define AHB_OFFSET 0x200
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#define BASE_HSUSB 0xE6590000
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#define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */
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#define SUSPM 0x4000
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#define SUSPM_NORMAL BIT(14)
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#define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */
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#define USB0SEL 0x00000030
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#define USB0SEL_EHCI 0x00000010
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#define SMSTPCR7 0xE615014C
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#define SMSTPCR700 BIT(0) /* EHCI3 */
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#define SMSTPCR701 BIT(1) /* EHCI2 */
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#define SMSTPCR702 BIT(2) /* EHCI1 */
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#define SMSTPCR703 BIT(3) /* EHCI0 */
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#define SMSTPCR704 BIT(4) /* HSUSB */
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#define AHB_PLL_RST BIT(1)
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#define USBH_INTBEN BIT(2)
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#define USBH_INTAEN BIT(1)
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#define AHB_INT_ENABLE 0x200
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#define AHB_USBCTR 0x20c
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int ehci_hcd_stop(int index)
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{
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#if defined(CONFIG_R8A7795)
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const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
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#else
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const u32 mask = SMSTPCR703 | SMSTPCR702;
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#endif
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const u32 base = RCAR_GEN3_USB_BASE(index);
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int ret;
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/* Reset EHCI */
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setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
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ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
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CMD_RESET, false, 10, true);
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if (ret) {
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printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
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index, ret);
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}
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setbits_le32(SMSTPCR7, BIT(3 - index));
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if ((readl(SMSTPCR7) & mask) == mask)
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setbits_le32(SMSTPCR7, SMSTPCR704);
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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const void __iomem *base =
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(void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
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struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
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clrbits_le32(SMSTPCR7, BIT(3 - index));
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clrbits_le32(SMSTPCR7, SMSTPCR704);
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*hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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/* Enable interrupt */
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setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
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writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
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writel(0x000209ab, base + CORE_OC_TIMSET);
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/* Choice USB0SEL */
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clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
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/* Clock & Reset */
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clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
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/* low power status */
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clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
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return 0;
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}
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