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The DP83867 when not properly bootstrapped - especially with LED_0 pin - can enter N/A MODE4 for "port mirroring" feature. To provide normal operation of the PHY, one needs not only to explicitly disable the port mirroring feature, but as well stop some IC internal testing (which disables RGMII communication). To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit 11 examined. When it is set, the another RESERVED bit (11) at PHYCR (0x0010) register must be clear to disable testing mode and enable RGMII communication. Thorough explanation of the problem can be found at following e2e thread: "DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - Linux driver" https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954 Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring" N/A MODE4") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Lukasz Majewski <lukma@denx.de> |
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| .. | ||
| aquantia.c | ||
| atheros.c | ||
| b53.c | ||
| broadcom.c | ||
| cortina.c | ||
| davicom.c | ||
| et1011c.c | ||
| fixed.c | ||
| generic_10g.c | ||
| Kconfig | ||
| lxt.c | ||
| Makefile | ||
| marvell.c | ||
| meson-gxl.c | ||
| micrel_ksz8xxx.c | ||
| micrel_ksz90x1.c | ||
| miiphybb.c | ||
| mscc.c | ||
| mv88e61xx.c | ||
| mv88e6352.c | ||
| natsemi.c | ||
| phy.c | ||
| realtek.c | ||
| smsc.c | ||
| teranetics.c | ||
| ti.c | ||
| vitesse.c | ||
| xilinx_phy.c | ||