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https://github.com/brain-hackers/u-boot-brain
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6eb15e50f4
ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
42 lines
887 B
C
42 lines
887 B
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARC_CACHE_H
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#define __ASM_ARC_CACHE_H
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#include <config.h>
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#ifdef CONFIG_ARC_CACHE_LINE_SHIFT
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#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT)
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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/* Satisfy users of ARCH_DMA_MINALIGN */
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#define ARCH_DMA_MINALIGN 128
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#endif
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#if defined(ARC_MMU_ABSENT)
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#define CONFIG_ARC_MMU_VER 0
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#elif defined(CONFIG_ARC_MMU_V4)
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#define CONFIG_ARC_MMU_VER 4
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#endif
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_ISA_ARCV2
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void slc_enable(void);
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void slc_disable(void);
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void slc_flush(void);
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void slc_invalidate(void);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARC_CACHE_H */
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