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![Simon Glass](/assets/img/avatar_default.png)
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
199 lines
5.0 KiB
C
199 lines
5.0 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Qualcomm SPMI bus driver
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* Loosely based on Little Kernel driver
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <spmi/spmi.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PMIC Arbiter configuration registers */
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#define PMIC_ARB_VERSION 0x0000
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#define PMIC_ARB_VERSION_V2_MIN 0x20010000
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#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
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#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
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#define SPMI_REG_CMD0 0x0
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#define SPMI_REG_CONFIG 0x4
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#define SPMI_REG_STATUS 0x8
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#define SPMI_REG_WDATA 0x10
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#define SPMI_REG_RDATA 0x18
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#define SPMI_CMD_OPCODE_SHIFT 27
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#define SPMI_CMD_SLAVE_ID_SHIFT 20
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#define SPMI_CMD_ADDR_SHIFT 12
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#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
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#define SPMI_CMD_BYTE_CNT_SHIFT 0
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#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
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#define SPMI_CMD_EXT_REG_READ_LONG 0x01
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#define SPMI_STATUS_DONE 0x1
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#define SPMI_MAX_CHANNELS 128
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#define SPMI_MAX_SLAVES 16
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#define SPMI_MAX_PERIPH 256
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struct msm_spmi_priv {
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phys_addr_t arb_chnl; /* ARB channel mapping base */
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phys_addr_t spmi_core; /* SPMI core */
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phys_addr_t spmi_obs; /* SPMI observer */
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/* SPMI channel map */
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uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
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};
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static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
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uint8_t val)
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{
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struct msm_spmi_priv *priv = dev_get_priv(dev);
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unsigned channel;
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uint32_t reg = 0;
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if (usid >= SPMI_MAX_SLAVES)
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return -EIO;
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if (pid >= SPMI_MAX_PERIPH)
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return -EIO;
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channel = priv->channel_map[usid][pid];
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/* Disable IRQ mode for the current channel*/
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writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
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SPMI_REG_CONFIG);
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/* Write single byte */
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writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
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/* Prepare write command */
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reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
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reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
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reg |= (pid << SPMI_CMD_ADDR_SHIFT);
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reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
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reg |= 1; /* byte count */
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/* Send write command */
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writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
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/* Wait till CMD DONE status */
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reg = 0;
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while (!reg) {
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reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
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SPMI_REG_STATUS);
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}
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if (reg ^ SPMI_STATUS_DONE) {
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printf("SPMI write failure.\n");
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return -EIO;
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}
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return 0;
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}
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static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
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{
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struct msm_spmi_priv *priv = dev_get_priv(dev);
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unsigned channel;
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uint32_t reg = 0;
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if (usid >= SPMI_MAX_SLAVES)
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return -EIO;
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if (pid >= SPMI_MAX_PERIPH)
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return -EIO;
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channel = priv->channel_map[usid][pid];
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/* Disable IRQ mode for the current channel*/
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writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
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/* Prepare read command */
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reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
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reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
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reg |= (pid << SPMI_CMD_ADDR_SHIFT);
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reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
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reg |= 1; /* byte count */
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/* Request read */
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writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
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/* Wait till CMD DONE status */
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reg = 0;
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while (!reg) {
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reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
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SPMI_REG_STATUS);
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}
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if (reg ^ SPMI_STATUS_DONE) {
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printf("SPMI read failure.\n");
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return -EIO;
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}
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/* Read the data */
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return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
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SPMI_REG_RDATA) & 0xFF;
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}
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static struct dm_spmi_ops msm_spmi_ops = {
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.read = msm_spmi_read,
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.write = msm_spmi_write,
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};
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static int msm_spmi_probe(struct udevice *dev)
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{
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struct udevice *parent = dev->parent;
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struct msm_spmi_priv *priv = dev_get_priv(dev);
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int node = dev_of_offset(dev);
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u32 hw_ver;
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bool is_v1;
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int i;
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priv->arb_chnl = dev_read_addr(dev);
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priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
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dev_of_offset(parent), node, "reg", 1, NULL, false);
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priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
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dev_of_offset(parent), node, "reg", 2, NULL, false);
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hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
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is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
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dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
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if (priv->arb_chnl == FDT_ADDR_T_NONE ||
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priv->spmi_core == FDT_ADDR_T_NONE ||
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priv->spmi_obs == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Scan peripherals connected to each SPMI channel */
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for (i = 0; i < SPMI_MAX_PERIPH ; i++) {
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uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
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uint8_t slave_id = (periph & 0xf0000) >> 16;
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uint8_t pid = (periph & 0xff00) >> 8;
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priv->channel_map[slave_id][pid] = i;
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}
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return 0;
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}
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static const struct udevice_id msm_spmi_ids[] = {
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{ .compatible = "qcom,spmi-pmic-arb" },
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{ }
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};
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U_BOOT_DRIVER(msm_spmi) = {
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.name = "msm_spmi",
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.id = UCLASS_SPMI,
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.of_match = msm_spmi_ids,
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.ops = &msm_spmi_ops,
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.probe = msm_spmi_probe,
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.priv_auto = sizeof(struct msm_spmi_priv),
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};
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