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![Simon Glass](/assets/img/avatar_default.png)
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
424 lines
9.5 KiB
C
424 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <generic-phy.h>
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#include <log.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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/* USBPHYC registers */
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#define STM32_USBPHYC_PLL 0x0
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#define STM32_USBPHYC_MISC 0x8
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/* STM32_USBPHYC_PLL bit fields */
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#define PLLNDIV GENMASK(6, 0)
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#define PLLNDIV_SHIFT 0
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#define PLLFRACIN GENMASK(25, 10)
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#define PLLFRACIN_SHIFT 10
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#define PLLEN BIT(26)
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#define PLLSTRB BIT(27)
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#define PLLSTRBYP BIT(28)
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#define PLLFRACCTL BIT(29)
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#define PLLDITHEN0 BIT(30)
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#define PLLDITHEN1 BIT(31)
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/* STM32_USBPHYC_MISC bit fields */
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#define SWITHOST BIT(0)
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#define MAX_PHYS 2
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/* max 100 us for PLL lock and 100 us for PHY init */
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#define PLL_INIT_TIME_US 200
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#define PLL_PWR_DOWN_TIME_US 5
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#define PLL_FVCO 2880 /* in MHz */
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#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
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#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
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struct pll_params {
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u8 ndiv;
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u16 frac;
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};
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struct stm32_usbphyc {
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fdt_addr_t base;
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struct clk clk;
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struct udevice *vdda1v1;
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struct udevice *vdda1v8;
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struct stm32_usbphyc_phy {
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struct udevice *vdd;
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struct udevice *vbus;
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bool init;
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bool powered;
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} phys[MAX_PHYS];
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};
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static void stm32_usbphyc_get_pll_params(u32 clk_rate,
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struct pll_params *pll_params)
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{
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unsigned long long fvco, ndiv, frac;
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/*
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* | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
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* | FVCO = 2880MHz
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* | NDIV = integer part of input bits to set the LDF
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* | FRACT = fractional part of input bits to set the LDF
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* => PLLNDIV = integer part of (FVCO / (INFF*2))
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* => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
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* <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
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*/
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fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
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ndiv = fvco;
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do_div(ndiv, (clk_rate * 2));
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pll_params->ndiv = (u8)ndiv;
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frac = fvco * (1 << 16);
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do_div(frac, (clk_rate * 2));
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frac = frac - (ndiv * (1 << 16));
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pll_params->frac = (u16)frac;
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}
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static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
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{
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struct pll_params pll_params;
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u32 clk_rate = clk_get_rate(&usbphyc->clk);
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u32 usbphyc_pll;
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if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
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pr_debug("%s: input clk freq (%dHz) out of range\n",
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__func__, clk_rate);
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return -EINVAL;
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}
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stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
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usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
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usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
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if (pll_params.frac) {
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usbphyc_pll |= PLLFRACCTL;
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usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
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& PLLFRACIN);
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}
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writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
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pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
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clk_rate, pll_params.ndiv, pll_params.frac);
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return 0;
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}
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static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
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{
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int i;
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for (i = 0; i < MAX_PHYS; i++) {
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if (usbphyc->phys[i].init)
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return true;
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}
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return false;
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}
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static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
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{
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int i;
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for (i = 0; i < MAX_PHYS; i++) {
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if (usbphyc->phys[i].powered)
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return true;
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}
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return false;
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}
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static int stm32_usbphyc_phy_init(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
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true : false;
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int ret;
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pr_debug("%s phy ID = %lu\n", __func__, phy->id);
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/* Check if one phy port has already configured the pll */
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if (pllen && stm32_usbphyc_is_init(usbphyc))
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goto initialized;
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if (usbphyc->vdda1v1) {
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ret = regulator_set_enable(usbphyc->vdda1v1, true);
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if (ret)
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return ret;
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}
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if (usbphyc->vdda1v8) {
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ret = regulator_set_enable(usbphyc->vdda1v8, true);
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if (ret)
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return ret;
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}
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if (pllen) {
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clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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udelay(PLL_PWR_DOWN_TIME_US);
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}
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ret = stm32_usbphyc_pll_init(usbphyc);
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if (ret)
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return ret;
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setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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/* We must wait PLL_INIT_TIME_US before using PHY */
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udelay(PLL_INIT_TIME_US);
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if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
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return -EIO;
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initialized:
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usbphyc_phy->init = true;
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return 0;
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}
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static int stm32_usbphyc_phy_exit(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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int ret;
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pr_debug("%s phy ID = %lu\n", __func__, phy->id);
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usbphyc_phy->init = false;
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/* Check if other phy port requires pllen */
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if (stm32_usbphyc_is_init(usbphyc))
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return 0;
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clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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/*
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* We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
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* bit is still clear
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*/
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udelay(PLL_PWR_DOWN_TIME_US);
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if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
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return -EIO;
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if (usbphyc->vdda1v1) {
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ret = regulator_set_enable(usbphyc->vdda1v1, false);
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if (ret)
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return ret;
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}
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if (usbphyc->vdda1v8) {
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ret = regulator_set_enable(usbphyc->vdda1v8, false);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int stm32_usbphyc_phy_power_on(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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int ret;
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pr_debug("%s phy ID = %lu\n", __func__, phy->id);
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if (usbphyc_phy->vdd) {
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ret = regulator_set_enable(usbphyc_phy->vdd, true);
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if (ret)
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return ret;
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}
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if (usbphyc_phy->vbus) {
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ret = regulator_set_enable(usbphyc_phy->vbus, true);
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if (ret)
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return ret;
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}
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usbphyc_phy->powered = true;
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return 0;
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}
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static int stm32_usbphyc_phy_power_off(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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int ret;
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pr_debug("%s phy ID = %lu\n", __func__, phy->id);
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usbphyc_phy->powered = false;
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if (stm32_usbphyc_is_powered(usbphyc))
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return 0;
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if (usbphyc_phy->vbus) {
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ret = regulator_set_enable(usbphyc_phy->vbus, false);
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if (ret)
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return ret;
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}
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if (usbphyc_phy->vdd) {
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ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int stm32_usbphyc_get_regulator(ofnode node,
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char *supply_name,
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struct udevice **regulator)
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{
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struct ofnode_phandle_args regulator_phandle;
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int ret;
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ret = ofnode_parse_phandle_with_args(node, supply_name,
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NULL, 0, 0,
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®ulator_phandle);
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if (ret)
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return ret;
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ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
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regulator_phandle.node,
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regulator);
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if (ret)
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return ret;
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return 0;
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}
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static int stm32_usbphyc_of_xlate(struct phy *phy,
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struct ofnode_phandle_args *args)
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{
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if (args->args_count < 1)
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return -ENODEV;
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if (args->args[0] >= MAX_PHYS)
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return -ENODEV;
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phy->id = args->args[0];
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if ((phy->id == 0 && args->args_count != 1) ||
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(phy->id == 1 && args->args_count != 2)) {
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dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
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phy->id);
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return -EINVAL;
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}
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return 0;
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}
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static const struct phy_ops stm32_usbphyc_phy_ops = {
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.init = stm32_usbphyc_phy_init,
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.exit = stm32_usbphyc_phy_exit,
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.power_on = stm32_usbphyc_phy_power_on,
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.power_off = stm32_usbphyc_phy_power_off,
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.of_xlate = stm32_usbphyc_of_xlate,
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};
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static int stm32_usbphyc_probe(struct udevice *dev)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
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struct reset_ctl reset;
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ofnode node;
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int i, ret;
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usbphyc->base = dev_read_addr(dev);
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if (usbphyc->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Enable clock */
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ret = clk_get_by_index(dev, 0, &usbphyc->clk);
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if (ret)
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return ret;
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ret = clk_enable(&usbphyc->clk);
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if (ret)
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return ret;
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/* Reset */
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ret = reset_get_by_index(dev, 0, &reset);
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if (!ret) {
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reset_assert(&reset);
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udelay(2);
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reset_deassert(&reset);
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}
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/* get usbphyc regulator */
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ret = device_get_supply_regulator(dev, "vdda1v1-supply",
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&usbphyc->vdda1v1);
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if (ret) {
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dev_err(dev, "Can't get vdda1v1-supply regulator\n");
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return ret;
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}
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ret = device_get_supply_regulator(dev, "vdda1v8-supply",
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&usbphyc->vdda1v8);
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if (ret) {
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dev_err(dev, "Can't get vdda1v8-supply regulator\n");
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return ret;
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}
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/*
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* parse all PHY subnodes in order to populate regulator associated
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* to each PHY port
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*/
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node = dev_read_first_subnode(dev);
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for (i = 0; i < MAX_PHYS; i++) {
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
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usbphyc_phy->init = false;
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usbphyc_phy->powered = false;
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ret = stm32_usbphyc_get_regulator(node, "phy-supply",
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&usbphyc_phy->vdd);
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if (ret) {
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dev_err(dev, "Can't get phy-supply regulator\n");
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return ret;
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}
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ret = stm32_usbphyc_get_regulator(node, "vbus-supply",
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&usbphyc_phy->vbus);
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if (ret)
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usbphyc_phy->vbus = NULL;
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node = dev_read_next_subnode(node);
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}
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/* Check if second port has to be used for host controller */
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if (dev_read_bool(dev, "st,port2-switch-to-host"))
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setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
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return 0;
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}
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static const struct udevice_id stm32_usbphyc_of_match[] = {
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{ .compatible = "st,stm32mp1-usbphyc", },
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{ },
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};
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U_BOOT_DRIVER(stm32_usb_phyc) = {
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.name = "stm32-usbphyc",
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.id = UCLASS_PHY,
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.of_match = stm32_usbphyc_of_match,
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.ops = &stm32_usbphyc_phy_ops,
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.probe = stm32_usbphyc_probe,
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.priv_auto = sizeof(struct stm32_usbphyc),
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};
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