mirror of
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![Simon Glass](/assets/img/avatar_default.png)
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
638 lines
15 KiB
C
638 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* ocores-i2c.c: I2C bus driver for OpenCores I2C controller
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* (https://opencores.org/projects/i2c)
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*
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* (C) Copyright Peter Korsgaard <peter@korsgaard.com>
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*
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* Copyright (C) 2020 SiFive, Inc.
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*
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* Support for the GRLIB port of the controller by
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* Andreas Larsson <andreas@gaisler.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <i2c.h>
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#include <linux/io.h>
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#include <linux/compat.h>
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#include <linux/log2.h>
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#include <linux/delay.h>
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/* registers */
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#define OCI2C_PRELOW 0
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#define OCI2C_PREHIGH 1
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#define OCI2C_CONTROL 2
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#define OCI2C_DATA 3
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#define OCI2C_CMD 4 /* write only */
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#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
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#define OCI2C_CTRL_IEN 0x40
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#define OCI2C_CTRL_EN 0x80
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#define OCI2C_CMD_START 0x91
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#define OCI2C_CMD_STOP 0x41
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#define OCI2C_CMD_READ 0x21
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#define OCI2C_CMD_WRITE 0x11
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#define OCI2C_CMD_READ_ACK 0x21
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#define OCI2C_CMD_READ_NACK 0x29
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#define OCI2C_CMD_IACK 0x01
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#define OCI2C_STAT_IF 0x01
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#define OCI2C_STAT_TIP 0x02
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#define OCI2C_STAT_ARBLOST 0x20
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#define OCI2C_STAT_BUSY 0x40
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#define OCI2C_STAT_NACK 0x80
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#define STATE_DONE 0
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#define STATE_START 1
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#define STATE_WRITE 2
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#define STATE_READ 3
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#define STATE_ERROR 4
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#define TYPE_OCORES 0
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#define TYPE_GRLIB 1
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#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
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struct ocores_i2c_bus {
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void __iomem *base;
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u32 reg_shift;
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u32 reg_io_width;
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unsigned long flags;
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struct i2c_msg *msg;
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int pos;
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int nmsgs;
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int state; /* see STATE_ */
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struct clk clk;
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int ip_clk_khz;
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int bus_clk_khz;
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void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
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u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
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};
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DECLARE_GLOBAL_DATA_PTR;
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/* Boolean attribute values */
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enum {
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FALSE = 0,
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TRUE,
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};
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static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
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{
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writeb(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
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{
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writew(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
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{
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writel(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
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{
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out_be16(i2c->base + (reg << i2c->reg_shift), value);
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}
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static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
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{
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out_be32(i2c->base + (reg << i2c->reg_shift), value);
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}
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static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg)
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{
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return readb(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg)
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{
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return readw(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg)
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{
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return readl(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg)
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{
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return in_be16(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg)
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{
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return in_be32(i2c->base + (reg << i2c->reg_shift));
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}
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static inline void oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value)
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{
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i2c->setreg(i2c, reg, value);
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}
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static inline u8 oc_getreg(struct ocores_i2c_bus *i2c, int reg)
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{
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return i2c->getreg(i2c, reg);
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}
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static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
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{
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return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
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}
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static void ocores_process(struct ocores_i2c_bus *i2c, u8 stat)
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{
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struct i2c_msg *msg = i2c->msg;
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if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
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/* stop has been sent */
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
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return;
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}
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/* error? */
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if (stat & OCI2C_STAT_ARBLOST) {
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i2c->state = STATE_ERROR;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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return;
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}
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if (i2c->state == STATE_START || i2c->state == STATE_WRITE) {
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i2c->state =
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(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
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if (stat & OCI2C_STAT_NACK) {
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i2c->state = STATE_ERROR;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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return;
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}
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} else {
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msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
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}
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/* end of msg? */
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if (i2c->pos == msg->len) {
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i2c->nmsgs--;
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i2c->msg++;
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i2c->pos = 0;
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msg = i2c->msg;
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if (i2c->nmsgs) { /* end? */
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/* send start? */
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if (!(msg->flags & I2C_M_NOSTART)) {
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u8 addr = i2c_8bit_addr_from_msg(msg);
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i2c->state = STATE_START;
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oc_setreg(i2c, OCI2C_DATA, addr);
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
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return;
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}
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i2c->state = (msg->flags & I2C_M_RD)
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? STATE_READ : STATE_WRITE;
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} else {
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i2c->state = STATE_DONE;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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return;
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}
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}
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if (i2c->state == STATE_READ) {
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oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len - 1) ?
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OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
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} else {
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oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
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}
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}
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static irqreturn_t ocores_isr(int irq, void *dev_id)
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{
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struct ocores_i2c_bus *i2c = dev_id;
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u8 stat = oc_getreg(i2c, OCI2C_STATUS);
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if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
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if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
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return IRQ_NONE;
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} else if (!(stat & OCI2C_STAT_IF)) {
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return IRQ_NONE;
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}
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ocores_process(i2c, stat);
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return IRQ_HANDLED;
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}
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/**
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* Wait until something change in a given register
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* @i2c: ocores I2C device instance
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* @reg: register to query
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* @mask: bitmask to apply on register value
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* @val: expected result
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* @msec: timeout in msec
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*
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* Timeout is necessary to avoid to stay here forever when the chip
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* does not answer correctly.
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*
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* Return: 0 on success, -ETIMEDOUT on timeout
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*/
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static int ocores_wait(struct ocores_i2c_bus *i2c,
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int reg, u8 mask, u8 val,
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const unsigned long msec)
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{
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u32 count = 0;
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while (1) {
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u8 status = oc_getreg(i2c, reg);
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if ((status & mask) == val)
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break;
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udelay(1);
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count += 1;
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if (count == (1000 * msec))
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return -ETIMEDOUT;
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}
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return 0;
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}
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/**
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* Wait until is possible to process some data
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* @i2c: ocores I2C device instance
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*
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* Used when the device is in polling mode (interrupts disabled).
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*
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* Return: 0 on success, -ETIMEDOUT on timeout
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*/
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static int ocores_poll_wait(struct ocores_i2c_bus *i2c)
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{
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u8 mask;
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int err;
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if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
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/* transfer is over */
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mask = OCI2C_STAT_BUSY;
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} else {
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/* on going transfer */
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mask = OCI2C_STAT_TIP;
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/*
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* We wait for the data to be transferred (8bit),
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* then we start polling on the ACK/NACK bit
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*/
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udelay((8 * 1000) / i2c->bus_clk_khz);
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}
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/*
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* once we are here we expect to get the expected result immediately
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* so if after 1ms we timeout then something is broken.
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*/
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err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1);
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if (err)
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debug("%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
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__func__, mask);
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return err;
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}
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/**
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* It handles an IRQ-less transfer
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* @i2c: ocores I2C device instance
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*
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* Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
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* (only that IRQ are not produced). This means that we can re-use entirely
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* ocores_isr(), we just add our polling code around it.
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*
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* It can run in atomic context
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*/
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static void ocores_process_polling(struct ocores_i2c_bus *i2c)
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{
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while (1) {
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irqreturn_t ret;
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int err;
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err = ocores_poll_wait(i2c);
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if (err) {
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i2c->state = STATE_ERROR;
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break; /* timeout */
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}
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ret = ocores_isr(-1, i2c);
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if (ret == IRQ_NONE) {
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break; /* all messages have been transferred */
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} else {
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if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
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if (i2c->state == STATE_DONE)
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break;
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}
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}
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}
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static int ocores_xfer_core(struct ocores_i2c_bus *i2c,
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struct i2c_msg *msgs, int num, bool polling)
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{
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u8 ctrl;
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ctrl = oc_getreg(i2c, OCI2C_CONTROL);
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if (polling)
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oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
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i2c->msg = msgs;
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i2c->pos = 0;
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i2c->nmsgs = num;
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i2c->state = STATE_START;
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oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
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if (polling)
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ocores_process_polling(i2c);
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return (i2c->state == STATE_DONE) ? num : -EIO;
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}
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static int ocores_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
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{
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struct ocores_i2c_bus *bus = dev_get_priv(dev);
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int ret;
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debug("i2c_xfer: %d messages\n", nmsgs);
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ret = ocores_xfer_core(bus, msg, nmsgs, 1);
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if (ret != nmsgs) {
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debug("i2c_write: error sending\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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static int ocores_i2c_enable_clk(struct udevice *dev)
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{
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struct ocores_i2c_bus *bus = dev_get_priv(dev);
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ulong clk_rate;
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int ret;
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ret = clk_get_by_index(dev, 0, &bus->clk);
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if (ret)
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return -EINVAL;
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ret = clk_enable(&bus->clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&bus->clk);
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if (!clk_rate)
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return -EINVAL;
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bus->ip_clk_khz = clk_rate / 1000;
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clk_free(&bus->clk);
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return 0;
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}
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static int ocores_init(struct udevice *dev, struct ocores_i2c_bus *bus)
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{
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int prescale;
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int diff;
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u8 ctrl = oc_getreg(bus, OCI2C_CONTROL);
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/* make sure the device is disabled */
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ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
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oc_setreg(bus, OCI2C_CONTROL, ctrl);
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prescale = (bus->ip_clk_khz / (5 * bus->bus_clk_khz)) - 1;
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prescale = clamp(prescale, 0, 0xffff);
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diff = bus->ip_clk_khz / (5 * (prescale + 1)) - bus->bus_clk_khz;
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if (abs(diff) > bus->bus_clk_khz / 10) {
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debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
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bus->ip_clk_khz, bus->bus_clk_khz);
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return -EINVAL;
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}
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oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
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oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
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/* Init the device */
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oc_setreg(bus, OCI2C_CMD, OCI2C_CMD_IACK);
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oc_setreg(bus, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
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return 0;
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}
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/*
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* Read and write functions for the GRLIB port of the controller. Registers are
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* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
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* register. The subsequent registers have their offsets decreased accordingly.
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*/
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static u8 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg)
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{
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u32 rd;
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int rreg = reg;
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if (reg != OCI2C_PRELOW)
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rreg--;
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rd = in_be32(i2c->base + (rreg << i2c->reg_shift));
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if (reg == OCI2C_PREHIGH)
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return (u8)(rd >> 8);
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else
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return (u8)rd;
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}
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static void oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value)
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{
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u32 curr, wr;
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int rreg = reg;
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if (reg != OCI2C_PRELOW)
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rreg--;
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if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
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curr = in_be32(i2c->base + (rreg << i2c->reg_shift));
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if (reg == OCI2C_PRELOW)
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wr = (curr & 0xff00) | value;
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else
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wr = (((u32)value) << 8) | (curr & 0xff);
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} else {
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wr = value;
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}
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out_be32(i2c->base + (rreg << i2c->reg_shift), wr);
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}
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static int ocores_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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{
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int prescale;
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int diff;
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struct ocores_i2c_bus *bus = dev_get_priv(dev);
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/* speed in Khz */
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speed = speed / 1000;
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prescale = (bus->ip_clk_khz / (5 * speed)) - 1;
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prescale = clamp(prescale, 0, 0xffff);
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diff = bus->ip_clk_khz / (5 * (prescale + 1)) - speed;
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if (abs(diff) > speed / 10) {
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debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
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bus->ip_clk_khz, speed);
|
|
return -EINVAL;
|
|
}
|
|
|
|
oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
|
|
oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
|
|
|
|
bus->bus_clk_khz = speed;
|
|
return 0;
|
|
}
|
|
|
|
int ocores_i2c_get_bus_speed(struct udevice *dev)
|
|
{
|
|
struct ocores_i2c_bus *bus = dev_get_priv(dev);
|
|
|
|
return (bus->bus_clk_khz * 1000);
|
|
}
|
|
|
|
static const struct dm_i2c_ops ocores_i2c_ops = {
|
|
.xfer = ocores_i2c_xfer,
|
|
.set_bus_speed = ocores_i2c_set_bus_speed,
|
|
.get_bus_speed = ocores_i2c_get_bus_speed,
|
|
};
|
|
|
|
static int ocores_i2c_probe(struct udevice *dev)
|
|
{
|
|
struct ocores_i2c_bus *bus = dev_get_priv(dev);
|
|
bool clock_frequency_present;
|
|
u32 val;
|
|
u32 clock_frequency_khz;
|
|
int ret;
|
|
|
|
bus->base = (void __iomem *)devfdt_get_addr(dev);
|
|
|
|
if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) {
|
|
/* no 'reg-shift', check for deprecated 'regstep' */
|
|
ret = dev_read_u32(dev, "regstep", &val);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"missing both reg-shift and regstep property: %d\n", ret);
|
|
return -EINVAL;
|
|
} else {
|
|
bus->reg_shift = ilog2(val);
|
|
dev_warn(dev,
|
|
"regstep property deprecated, use reg-shift\n");
|
|
}
|
|
}
|
|
|
|
if (dev_read_u32(dev, "clock-frequency", &val)) {
|
|
bus->bus_clk_khz = 100;
|
|
clock_frequency_present = FALSE;
|
|
} else {
|
|
bus->bus_clk_khz = val / 1000;
|
|
clock_frequency_khz = val / 1000;
|
|
clock_frequency_present = TRUE;
|
|
}
|
|
|
|
ret = ocores_i2c_enable_clk(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (bus->ip_clk_khz == 0) {
|
|
if (dev_read_u32(dev, "opencores,ip-clock-frequency", &val)) {
|
|
if (!clock_frequency_present) {
|
|
dev_err(dev,
|
|
"Missing required parameter 'opencores,ip-clock-frequency'\n");
|
|
clk_disable(&bus->clk);
|
|
return -ENODEV;
|
|
}
|
|
|
|
bus->ip_clk_khz = clock_frequency_khz;
|
|
dev_warn(dev,
|
|
"Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
|
|
} else {
|
|
bus->ip_clk_khz = val / 1000;
|
|
if (clock_frequency_present)
|
|
bus->bus_clk_khz = clock_frequency_khz;
|
|
}
|
|
}
|
|
|
|
bus->reg_io_width = dev_read_u32_default(dev, "reg-io-width", 1);
|
|
|
|
if (dev_get_driver_data(dev) == TYPE_GRLIB) {
|
|
debug("GRLIB variant of i2c-ocores\n");
|
|
bus->setreg = oc_setreg_grlib;
|
|
bus->getreg = oc_getreg_grlib;
|
|
}
|
|
|
|
if (!bus->setreg || !bus->getreg) {
|
|
bool be = (cpu_to_be32(0x12345678) == 0x12345678);
|
|
|
|
switch (bus->reg_io_width) {
|
|
case 1:
|
|
bus->setreg = oc_setreg_8;
|
|
bus->getreg = oc_getreg_8;
|
|
break;
|
|
|
|
case 2:
|
|
bus->setreg = be ? oc_setreg_16be : oc_setreg_16;
|
|
bus->getreg = be ? oc_getreg_16be : oc_getreg_16;
|
|
break;
|
|
|
|
case 4:
|
|
bus->setreg = be ? oc_setreg_32be : oc_setreg_32;
|
|
bus->getreg = be ? oc_getreg_32be : oc_getreg_32;
|
|
break;
|
|
|
|
default:
|
|
debug("Unsupported I/O width (%d)\n",
|
|
bus->reg_io_width);
|
|
ret = -EINVAL;
|
|
goto err_clk;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set OCORES_FLAG_BROKEN_IRQ to enable workaround for
|
|
* FU540-C000 SoC in polling mode.
|
|
* Since the SoC does have an interrupt, its DT has an interrupt
|
|
* property - But this should be bypassed as the IRQ logic in this
|
|
* SoC is broken.
|
|
*/
|
|
|
|
if (device_is_compatible(dev, "sifive,fu540-c000-i2c"))
|
|
bus->flags |= OCORES_FLAG_BROKEN_IRQ;
|
|
|
|
ret = ocores_init(dev, bus);
|
|
if (ret)
|
|
goto err_clk;
|
|
|
|
return 0;
|
|
|
|
err_clk:
|
|
clk_disable(&bus->clk);
|
|
return ret;
|
|
}
|
|
|
|
static const struct udevice_id ocores_i2c_ids[] = {
|
|
{ .compatible = "opencores,i2c-ocores", .data = TYPE_OCORES },
|
|
{ .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB },
|
|
{ .compatible = "sifive,fu540-c000-i2c" },
|
|
{ .compatible = "sifive,i2c0" },
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_ocores) = {
|
|
.name = "i2c_ocores",
|
|
.id = UCLASS_I2C,
|
|
.of_match = ocores_i2c_ids,
|
|
.probe = ocores_i2c_probe,
|
|
.priv_auto = sizeof(struct ocores_i2c_bus),
|
|
.ops = &ocores_i2c_ops,
|
|
};
|