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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
220 lines
5.1 KiB
C
220 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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struct uniphier_i2c_regs {
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u32 dtrm; /* data transmission */
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#define I2C_DTRM_STA (1 << 10)
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#define I2C_DTRM_STO (1 << 9)
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#define I2C_DTRM_NACK (1 << 8)
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#define I2C_DTRM_RD (1 << 0)
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u32 drec; /* data reception */
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#define I2C_DREC_STS (1 << 12)
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#define I2C_DREC_LRB (1 << 11)
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#define I2C_DREC_LAB (1 << 9)
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u32 myad; /* slave address */
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u32 clk; /* clock frequency control */
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u32 brst; /* bus reset */
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#define I2C_BRST_FOEN (1 << 1)
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#define I2C_BRST_BRST (1 << 0)
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u32 hold; /* hold time control */
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u32 bsts; /* bus status monitor */
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u32 noise; /* noise filter control */
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u32 setup; /* setup time control */
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};
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#define IOBUS_FREQ 100000000
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struct uniphier_i2c_priv {
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struct udevice *dev;
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struct uniphier_i2c_regs __iomem *regs; /* register base */
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unsigned long input_clk; /* master clock (Hz) */
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unsigned long wait_us; /* wait for every byte transfer (us) */
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};
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static int uniphier_i2c_probe(struct udevice *dev)
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{
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fdt_addr_t addr;
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struct uniphier_i2c_priv *priv = dev_get_priv(dev);
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = devm_ioremap(dev, addr, SZ_64);
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if (!priv->regs)
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return -ENOMEM;
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priv->input_clk = IOBUS_FREQ;
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priv->dev = dev;
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/* deassert reset */
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writel(0x3, &priv->regs->brst);
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return 0;
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}
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static int send_and_recv_byte(struct uniphier_i2c_priv *priv, u32 dtrm)
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{
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writel(dtrm, &priv->regs->dtrm);
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/*
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* This controller only provides interruption to inform the completion
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* of each byte transfer. (No status register to poll it.)
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* Unfortunately, U-Boot does not have a good support of interrupt.
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* Wait for a while.
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*/
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udelay(priv->wait_us);
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return readl(&priv->regs->drec);
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}
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static int send_byte(struct uniphier_i2c_priv *priv, u32 dtrm, bool *stop)
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{
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int ret = 0;
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u32 drec;
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drec = send_and_recv_byte(priv, dtrm);
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if (drec & I2C_DREC_LAB) {
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dev_dbg(priv->dev, "uniphier_i2c: bus arbitration failed\n");
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*stop = false;
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ret = -EREMOTEIO;
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}
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if (drec & I2C_DREC_LRB) {
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dev_dbg(priv->dev, "uniphier_i2c: slave did not return ACK\n");
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ret = -EREMOTEIO;
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}
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return ret;
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}
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static int uniphier_i2c_transmit(struct uniphier_i2c_priv *priv, uint addr,
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uint len, const u8 *buf, bool *stop)
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{
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int ret;
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dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
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ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop);
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if (ret < 0)
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goto fail;
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while (len--) {
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ret = send_byte(priv, I2C_DTRM_NACK | *buf++, stop);
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if (ret < 0)
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goto fail;
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}
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fail:
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if (*stop)
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writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
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return ret;
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}
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static int uniphier_i2c_receive(struct uniphier_i2c_priv *priv, uint addr,
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uint len, u8 *buf, bool *stop)
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{
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int ret;
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dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
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ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK |
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I2C_DTRM_RD | addr << 1, stop);
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if (ret < 0)
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goto fail;
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while (len--)
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*buf++ = send_and_recv_byte(priv, len ? 0 : I2C_DTRM_NACK);
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fail:
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if (*stop)
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writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
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return ret;
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}
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static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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{
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int ret = 0;
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struct uniphier_i2c_priv *priv = dev_get_priv(bus);
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bool stop;
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for (; nmsgs > 0; nmsgs--, msg++) {
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/* If next message is read, skip the stop condition */
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stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
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if (msg->flags & I2C_M_RD)
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ret = uniphier_i2c_receive(priv, msg->addr, msg->len,
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msg->buf, &stop);
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else
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ret = uniphier_i2c_transmit(priv, msg->addr, msg->len,
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msg->buf, &stop);
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if (ret < 0)
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break;
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}
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return ret;
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}
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static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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struct uniphier_i2c_priv *priv = dev_get_priv(bus);
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/* max supported frequency is 400 kHz */
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if (speed > I2C_SPEED_FAST_RATE)
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return -EINVAL;
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/* bus reset: make sure the bus is idle when change the frequency */
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writel(0x1, &priv->regs->brst);
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writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed),
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&priv->regs->clk);
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writel(0x3, &priv->regs->brst);
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/*
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* Theoretically, each byte can be transferred in
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* 1000000 * 9 / speed usec. For safety, wait more than double.
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*/
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priv->wait_us = 20000000 / speed;
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return 0;
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}
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static const struct dm_i2c_ops uniphier_i2c_ops = {
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.xfer = uniphier_i2c_xfer,
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.set_bus_speed = uniphier_i2c_set_bus_speed,
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};
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static const struct udevice_id uniphier_i2c_of_match[] = {
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{ .compatible = "socionext,uniphier-i2c" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_i2c) = {
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.name = "uniphier-i2c",
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.id = UCLASS_I2C,
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.of_match = uniphier_i2c_of_match,
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.probe = uniphier_i2c_probe,
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.priv_auto = sizeof(struct uniphier_i2c_priv),
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.ops = &uniphier_i2c_ops,
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};
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