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https://github.com/brain-hackers/u-boot-brain
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bcc1726a7b
ATF(ARM Trusted Firmware) is used by ARM arch64 SoCs, find more infomation about ATF at: https://github.com/ARM-software/arm-trusted-firmware SPL is considered as BL2 in ATF terminology, it needs to load other parts of ATF binary like BL31, BL32, SCP-BL30, and BL33(U-Boot). And needs to prepare the parameter for BL31 which including entry and image information for all other images. Then the SPL handle PC to BL31 with the parameter, the BL31 will do the rest of work and at last get into U-Boot(BL33). This patch needs work with patches from Andre for SPL support multi binary in FIT. The entry point of bl31 and bl33 are still using hard code because we still can not get them from the FIT image information. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
/*
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* Reference to the ARM TF Project,
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* plat/arm/common/arm_bl2_setup.c
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* Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
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* reserved.
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* Copyright (C) 2016 Rockchip Electronic Co.,Ltd
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* Written by Kever Yang <kever.yang@rock-chips.com>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common.h>
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#include <atf_common.h>
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#include <errno.h>
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#include <spl.h>
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static struct bl2_to_bl31_params_mem bl31_params_mem;
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static struct bl31_params *bl2_to_bl31_params;
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/**
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* bl2_plat_get_bl31_params() - prepare params for bl31.
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*
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* This function assigns a pointer to the memory that the platform has kept
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* aside to pass platform specific and trusted firmware related information
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* to BL31. This memory is allocated by allocating memory to
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* bl2_to_bl31_params_mem structure which is a superset of all the
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* structure whose information is passed to BL31
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* NOTE: This function should be called only once and should be done
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* before generating params to BL31
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*
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* @return bl31 params structure pointer
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*/
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struct bl31_params *bl2_plat_get_bl31_params(void)
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{
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struct entry_point_info *bl33_ep_info;
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/*
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* Initialise the memory for all the arguments that needs to
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* be passed to BL31
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*/
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memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem));
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/* Assign memory for TF related information */
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bl2_to_bl31_params = &bl31_params_mem.bl31_params;
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SET_PARAM_HEAD(bl2_to_bl31_params, ATF_PARAM_BL31, ATF_VERSION_1, 0);
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/* Fill BL31 related information */
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SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
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ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
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/* Fill BL32 related information if it exists */
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#ifdef BL32_BASE
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bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP,
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ATF_VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
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ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
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#endif /* BL32_BASE */
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/* Fill BL33 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
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bl33_ep_info = &bl31_params_mem.bl33_ep_info;
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SET_PARAM_HEAD(bl33_ep_info, ATF_PARAM_EP, ATF_VERSION_1,
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ATF_EP_NON_SECURE);
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/* BL33 expects to receive the primary CPU MPID (through x0) */
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bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
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bl33_ep_info->pc = CONFIG_SYS_TEXT_BASE;
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bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXECPTIONS);
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info,
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ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
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return bl2_to_bl31_params;
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}
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void raw_write_daif(unsigned int daif)
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{
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__asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
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}
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void bl31_entry(void)
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{
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struct bl31_params *bl31_params;
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void (*entry)(struct bl31_params *params, void *plat_params) = NULL;
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bl31_params = bl2_plat_get_bl31_params();
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entry = (void *)CONFIG_SPL_ATF_TEXT_BASE;
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raw_write_daif(SPSR_EXCEPTION_MASK);
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dcache_disable();
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entry(bl31_params, NULL);
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}
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