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6875149740
P2020 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
58 lines
1.2 KiB
Plaintext
58 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P2020 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p2020-immr", "simple-bus";
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bus-frequency = <0x0>;
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
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compatible = "fsl,mpic";
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device_type = "open-pic";
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big-endian;
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single-cpu-affinity;
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last-interrupt-source = <255>;
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};
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};
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/* PCIe controller base address 0x8000 */
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&pci2 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
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law_trgt_if = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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};
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/* PCIe controller base address 0x9000 */
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&pci1 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
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law_trgt_if = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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};
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/* PCIe controller base address 0xa000 */
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&pci0 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
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law_trgt_if = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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};
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