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![Tom Rini](/assets/img/avatar_default.png)
- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>
105 lines
2.5 KiB
C
105 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <image.h>
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#include <asm/arch/reset_manager.h>
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#include <spl.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/nic301.h>
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#include <asm/sections.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#include <asm/arch/pinmux.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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u32 spl_boot_device(void)
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{
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const u32 bsel = readl(&sysmgr_regs->bootinfo);
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switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
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case 0x1: /* FPGA (HPS2FPGA Bridge) */
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return BOOT_DEVICE_RAM;
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case 0x2: /* NAND Flash (1.8V) */
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case 0x3: /* NAND Flash (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
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return BOOT_DEVICE_NAND;
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case 0x4: /* SD/MMC External Transceiver (1.8V) */
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case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
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socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
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return BOOT_DEVICE_MMC1;
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case 0x6: /* QSPI Flash (1.8V) */
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case 0x7: /* QSPI Flash (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
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return BOOT_DEVICE_SPI;
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default:
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printf("Invalid boot device (bsel=%08x)!\n", bsel);
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hang();
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}
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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u32 spl_boot_mode(const u32 boot_device)
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{
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#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
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return MMCSD_MODE_FS;
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#else
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return MMCSD_MODE_RAW;
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#endif
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}
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#endif
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void spl_board_init(void)
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{
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/* configuring the clock based on handoff */
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cm_basic_init(gd->fdt_blob);
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WATCHDOG_RESET();
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config_dedicated_pins(gd->fdt_blob);
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WATCHDOG_RESET();
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/* Release UART from reset */
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socfpga_reset_uart(0);
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/* enable console uart printing */
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preloader_console_init();
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}
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void board_init_f(ulong dummy)
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{
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/*
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* Configure Clock Manager to use intosc clock instead external osc to
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* ensure success watchdog operation. We do it as early as possible.
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*/
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cm_use_intosc();
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socfpga_watchdog_disable();
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arch_early_init_r();
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#ifdef CONFIG_HW_WATCHDOG
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/* release osc1 watchdog timer 0 from reset */
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socfpga_reset_deassert_osc1wd0();
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/* reconfigure and enable the watchdog */
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hw_watchdog_init();
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WATCHDOG_RESET();
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#endif /* CONFIG_HW_WATCHDOG */
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}
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