mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
638a058941
Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
34 lines
762 B
Plaintext
34 lines
762 B
Plaintext
CONFIG_X86=y
|
|
CONFIG_VENDOR_INTEL=y
|
|
CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
|
|
CONFIG_TARGET_BAYLEYBAY=y
|
|
CONFIG_HAVE_INTEL_ME=y
|
|
CONFIG_ENABLE_MRC_CACHE=y
|
|
CONFIG_SMP=y
|
|
CONFIG_HAVE_VGA_BIOS=y
|
|
CONFIG_VGA_BIOS_ADDR=0xfffa0000
|
|
CONFIG_GENERATE_PIRQ_TABLE=y
|
|
CONFIG_GENERATE_MP_TABLE=y
|
|
CONFIG_CMD_CPU=y
|
|
# CONFIG_CMD_IMLS is not set
|
|
# CONFIG_CMD_FLASH is not set
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
# CONFIG_CMD_NFS is not set
|
|
CONFIG_BOOTSTAGE=y
|
|
CONFIG_BOOTSTAGE_REPORT=y
|
|
CONFIG_CMD_BOOTSTAGE=y
|
|
CONFIG_OF_CONTROL=y
|
|
CONFIG_CPU=y
|
|
CONFIG_SPI_FLASH=y
|
|
CONFIG_DM_ETH=y
|
|
CONFIG_E1000=y
|
|
CONFIG_DM_PCI=y
|
|
CONFIG_DM_RTC=y
|
|
CONFIG_USB=y
|
|
CONFIG_DM_USB=y
|
|
CONFIG_VIDEO_VESA=y
|
|
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
|
|
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
|
|
CONFIG_USE_PRIVATE_LIBGCC=y
|
|
CONFIG_SYS_VSNPRINTF=y
|