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344ca0b40c
libata already has similar functions as implemented in the ahci code. Refactor the code to use the libata variants and remove the dependency on ata.h. Convert some defines to use the version from libata.h. Also, remove some unnecessary memset's of bss data. This is a step toward hopefully merging ahci.c and dw_ahsata.c which are essentially the same driver. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
162 lines
5.5 KiB
C
162 lines
5.5 KiB
C
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006.
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* Author: Jason Jin<Jason.jin@freescale.com>
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* Zhang Wei<wei.zhang@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _AHCI_H_
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#define _AHCI_H_
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#include <pci.h>
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#define AHCI_PCI_BAR 0x24
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#define AHCI_MAX_SG 56 /* hardware max is 64K */
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#define AHCI_CMD_SLOT_SZ 32
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#define AHCI_MAX_CMD_SLOT 32
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#define AHCI_RX_FIS_SZ 256
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#define AHCI_CMD_TBL_HDR 0x80
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#define AHCI_CMD_TBL_CDB 0x40
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#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
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#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
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AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
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#define AHCI_CMD_ATAPI (1 << 5)
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#define AHCI_CMD_WRITE (1 << 6)
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#define AHCI_CMD_PREFETCH (1 << 7)
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#define AHCI_CMD_RESET (1 << 8)
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#define AHCI_CMD_CLR_BUSY (1 << 10)
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#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
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/* Global controller registers */
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#define HOST_CAP 0x00 /* host capabilities */
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#define HOST_CTL 0x04 /* global host control */
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#define HOST_IRQ_STAT 0x08 /* interrupt status */
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#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
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#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
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#define HOST_CAP2 0x24 /* host capabilities, extended */
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/* HOST_CTL bits */
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#define HOST_RESET (1 << 0) /* reset controller; self-clear */
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#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
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#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
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/* Registers for each SATA port */
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#define PORT_LST_ADDR 0x00 /* command list DMA addr */
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#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
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#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
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#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
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#define PORT_IRQ_STAT 0x10 /* interrupt status */
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#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
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#define PORT_CMD 0x18 /* port command */
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#define PORT_TFDATA 0x20 /* taskfile data */
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#define PORT_SIG 0x24 /* device TF signature */
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#define PORT_CMD_ISSUE 0x38 /* command issue */
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#define PORT_SCR 0x28 /* SATA phy register block */
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#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
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#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
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#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
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#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
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/* PORT_IRQ_{STAT,MASK} bits */
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#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
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#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
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#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
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#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
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#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
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#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
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#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
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#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
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#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
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#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
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#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
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#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
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#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
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#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
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#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
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#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
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#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
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#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
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| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
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#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
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| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
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| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
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| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
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| PORT_IRQ_D2H_REG_FIS
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/* PORT_SCR_STAT bits */
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#define PORT_SCR_STAT_DET_MASK 0x3
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#define PORT_SCR_STAT_DET_COMINIT 0x1
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#define PORT_SCR_STAT_DET_PHYRDY 0x3
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/* PORT_CMD bits */
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#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
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#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
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#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
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#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
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#define PORT_CMD_CLO (1 << 3) /* Command list override */
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#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
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#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
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#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
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#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
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#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
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#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
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#define AHCI_MAX_PORTS 32
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#define ATA_FLAG_SATA (1 << 3)
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#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
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#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
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#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
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#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
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#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
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struct ahci_cmd_hdr {
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u32 opts;
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u32 status;
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u32 tbl_addr;
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u32 tbl_addr_hi;
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u32 reserved[4];
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};
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struct ahci_sg {
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u32 addr;
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u32 addr_hi;
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u32 reserved;
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u32 flags_size;
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};
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struct ahci_ioports {
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u32 cmd_addr;
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u32 scr_addr;
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u32 port_mmio;
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struct ahci_cmd_hdr *cmd_slot;
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struct ahci_sg *cmd_tbl_sg;
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u32 cmd_tbl;
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u32 rx_fis;
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};
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struct ahci_probe_ent {
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pci_dev_t dev;
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struct ahci_ioports port[AHCI_MAX_PORTS];
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u32 n_ports;
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u32 hard_port_no;
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u32 host_flags;
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u32 host_set_flags;
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u32 mmio_base;
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u32 pio_mask;
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u32 udma_mask;
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u32 flags;
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u32 cap; /* cache of HOST_CAP register */
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u32 port_map; /* cache of HOST_PORTS_IMPL reg */
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u32 link_port_map; /*linkup port map*/
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};
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int ahci_init(u32 base);
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#endif
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