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![York Sun](/assets/img/avatar_default.png)
The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
496 lines
14 KiB
C
496 lines
14 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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#include <asm/fsl_serdes.h>
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#include "../common/qixis.h"
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#include "../common/fman.h"
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#include "t4240qds_qixis.h"
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#define EMI_NONE 0xFFFFFFFF
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#define EMI1_RGMII 0
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#define EMI1_SLOT1 1
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#define EMI1_SLOT2 2
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#define EMI1_SLOT3 3
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#define EMI1_SLOT4 4
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#define EMI1_SLOT5 5
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#define EMI1_SLOT7 7
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#define EMI2 8 /* tmp, FIXME */
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/* Slot6 and Slot8 do not have EMI connections */
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static int mdio_mux[NUM_FM_PORTS];
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static const char *mdio_names[] = {
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"T4240QDS_MDIO0",
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"T4240QDS_MDIO1",
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"T4240QDS_MDIO2",
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"T4240QDS_MDIO3",
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"T4240QDS_MDIO4",
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"T4240QDS_MDIO5",
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"NULL",
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"T4240QDS_MDIO7",
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"T4240QDS_10GC",
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};
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static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
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static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
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static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u8 muxval)
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{
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struct mii_dev *bus;
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const char *name = t4240qds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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struct t4240qds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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static void t4240qds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if ((muxval < 6) || (muxval == 7)) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct t4240qds_mdio *priv = bus->priv;
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t4240qds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct t4240qds_mdio *priv = bus->priv;
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t4240qds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int t4240qds_mdio_reset(struct mii_dev *bus)
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{
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struct t4240qds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int t4240qds_mdio_init(char *realbusname, u8 muxval)
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{
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struct t4240qds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate T4240QDS MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate T4240QDS private data\n");
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free(bus);
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return -1;
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}
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bus->read = t4240qds_mdio_read;
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bus->write = t4240qds_mdio_write;
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bus->reset = t4240qds_mdio_reset;
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sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
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enum fm_port port, int offset)
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{
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if (mdio_mux[port] == EMI1_RGMII)
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fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
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/* TODO: will do with dts */
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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/* TODO: will do with dts */
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}
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FMAN_ENET)
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int i;
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struct memac_mdio_info dtsec_mdio_info;
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struct memac_mdio_info tgec_mdio_info;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_prtcl_s1, srds_prtcl_s2;
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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/* Initialize the mdio_mux array so we can recognize empty elements */
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for (i = 0; i < NUM_FM_PORTS; i++)
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mdio_mux[i] = EMI_NONE;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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tgec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the 10G MDIO bus */
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fm_memac_mdio_init(bis, &tgec_mdio_info);
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/* Register the muxing front-ends to the MDIO buses */
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t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
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t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
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t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
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t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
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t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
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t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
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t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
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t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
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switch (srds_prtcl_s1) {
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case 1:
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case 2:
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case 4:
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/* XAUI/HiGig in Slot1 and Slot2 */
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fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
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break;
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case 28:
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case 36:
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/* SGMII in Slot1 and Slot2 */
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
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if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
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fm_info_set_phy_address(FM1_DTSEC9,
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SGMII_CARD_PORT4_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10,
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SGMII_CARD_PORT3_PHY_ADDR);
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}
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break;
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case 38:
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fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
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if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
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fm_info_set_phy_address(FM1_DTSEC9,
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QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10,
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QSGMII_CARD_PHY_ADDR);
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}
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break;
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case 40:
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case 46:
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case 48:
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
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if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
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fm_info_set_phy_address(FM1_DTSEC10,
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SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC9,
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SGMII_CARD_PORT4_PHY_ADDR);
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}
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fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
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break;
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default:
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puts("Invalid SerDes1 protocol for T4240QDS\n");
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break;
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}
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1, lane, slot;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(FSL_SRDS_1,
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SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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break;
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slot = lane_to_slot_fsm1[lane];
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debug("FM1@DTSEC%u expects SGMII in slot %u\n",
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idx + 1, slot);
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if (QIXIS_READ(present2) & (1 << (slot - 1)))
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fm_disable_port(i);
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switch (slot) {
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case 1:
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mdio_mux[i] = EMI1_SLOT1;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 2:
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mdio_mux[i] = EMI1_SLOT2;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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};
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break;
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case PHY_INTERFACE_MODE_RGMII:
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/* FM1 DTSEC5 routes to RGMII with EC2 */
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debug("FM1@DTSEC%u is RGMII at address %u\n",
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idx + 1, 2);
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if (i == FM1_DTSEC5)
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fm_info_set_phy_address(i, 2);
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mdio_mux[i] = EMI1_RGMII;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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default:
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break;
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}
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}
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for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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mdio_mux[i] = EMI2;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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default:
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break;
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}
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}
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#if (CONFIG_SYS_NUM_FMAN == 2)
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switch (srds_prtcl_s2) {
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case 1:
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case 2:
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case 4:
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/* XAUI/HiGig in Slot3 and Slot4 */
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fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
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fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
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break;
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case 7:
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case 13:
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case 14:
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case 16:
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case 22:
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case 23:
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case 25:
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case 26:
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/* XAUI/HiGig in Slot3, SGMII in Slot4 */
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fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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case 28:
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case 36:
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/* SGMII in Slot3 and Slot4 */
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fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
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break;
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case 38:
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/* QSGMII in Slot3 and Slot4 */
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fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
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break;
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case 40:
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case 46:
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case 48:
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/* SGMII in Slot3 */
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fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
|
|
/* QSGMII in Slot4 */
|
|
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
|
|
break;
|
|
case 50:
|
|
case 52:
|
|
case 54:
|
|
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
|
|
break;
|
|
case 56:
|
|
case 57:
|
|
/* XFI in Slot3, SGMII in Slot4 */
|
|
fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
|
|
fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
|
|
break;
|
|
default:
|
|
puts("Invalid SerDes2 protocol for T4240QDS\n");
|
|
break;
|
|
}
|
|
|
|
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
|
|
int idx = i - FM2_DTSEC1, lane, slot;
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
lane = serdes_get_first_lane(FSL_SRDS_2,
|
|
SGMII_FM2_DTSEC1 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot_fsm2[lane];
|
|
debug("FM2@DTSEC%u expects SGMII in slot %u\n",
|
|
idx + 1, slot);
|
|
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
switch (slot) {
|
|
case 3:
|
|
mdio_mux[i] = EMI1_SLOT3;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
case 4:
|
|
mdio_mux[i] = EMI1_SLOT4;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
};
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
/*
|
|
* If DTSEC5 is RGMII, then it's routed via via EC1 to
|
|
* the first on-board RGMII port. If DTSEC6 is RGMII,
|
|
* then it's routed via via EC2 to the second on-board
|
|
* RGMII port.
|
|
*/
|
|
debug("FM2@DTSEC%u is RGMII at address %u\n",
|
|
idx + 1, i == FM2_DTSEC5 ? 1 : 2);
|
|
fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
|
|
mdio_mux[i] = EMI1_RGMII;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_XGMII:
|
|
mdio_mux[i] = EMI2;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif /* CONFIG_SYS_NUM_FMAN */
|
|
|
|
cpu_eth_init(bis);
|
|
#endif /* CONFIG_FMAN_ENET */
|
|
|
|
return pci_eth_init(bis);
|
|
}
|