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![Mateusz Kulikowski](/assets/img/avatar_default.png)
First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code: - Reset controller (PSHOLD) - Clock controller (very simple clock configuration for MMC and UART) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
41 lines
772 B
C
41 lines
772 B
C
/*
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* Qualcomm APQ8016 reset controller driver
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <reset.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int msm_reset_request(struct udevice *dev, enum reset_t type)
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{
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phys_addr_t addr = dev_get_addr(dev);
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if (!addr)
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return -EINVAL;
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writel(0, addr);
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return -EINPROGRESS;
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}
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static struct reset_ops msm_reset_ops = {
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.request = msm_reset_request,
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};
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static const struct udevice_id msm_reset_ids[] = {
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{ .compatible = "qcom,pshold" },
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{ }
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};
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U_BOOT_DRIVER(msm_reset) = {
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.name = "msm_reset",
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.id = UCLASS_RESET,
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.of_match = msm_reset_ids,
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.ops = &msm_reset_ops,
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};
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