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https://github.com/brain-hackers/u-boot-brain
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![Jagan Teki](/assets/img/avatar_default.png)
It is not much needed to print nand size in SPL during nand boot, and most of nand spl drivers doesn't print the same. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
230 lines
5.9 KiB
C
230 lines
5.9 KiB
C
/*
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* Copyright (C) 2014 Gateworks Corporation
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <malloc.h>
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static struct mtd_info *mtd;
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static struct nand_chip nand_chip;
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static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
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int column, int page_addr)
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{
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register struct nand_chip *chip = mtd_to_nand(mtd);
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u32 timeo, time_start;
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/* write out the command to the device */
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chip->cmd_ctrl(mtd, command, NAND_CLE);
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/* Serially input address */
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if (column != -1) {
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chip->cmd_ctrl(mtd, column, NAND_ALE);
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chip->cmd_ctrl(mtd, column >> 8, NAND_ALE);
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}
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if (page_addr != -1) {
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chip->cmd_ctrl(mtd, page_addr, NAND_ALE);
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chip->cmd_ctrl(mtd, page_addr >> 8, NAND_ALE);
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/* One more address cycle for devices > 128MiB */
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if (chip->chipsize > (128 << 20))
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chip->cmd_ctrl(mtd, page_addr >> 16, NAND_ALE);
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}
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0);
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if (command == NAND_CMD_READ0) {
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chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE);
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0);
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}
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/* wait for nand ready */
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ndelay(100);
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timeo = (CONFIG_SYS_HZ * 20) / 1000;
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time_start = get_timer(0);
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while (get_timer(time_start) < timeo) {
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if (chip->dev_ready(mtd))
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break;
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}
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}
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static int mxs_flash_ident(struct mtd_info *mtd)
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{
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register struct nand_chip *chip = mtd_to_nand(mtd);
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int i;
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u8 mfg_id, dev_id;
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u8 id_data[8];
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struct nand_onfi_params *p = &chip->onfi_params;
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/* Reset the chip */
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chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
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/* Send the command for reading device ID */
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chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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/* Read manufacturer and device IDs */
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mfg_id = chip->read_byte(mtd);
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dev_id = chip->read_byte(mtd);
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/* Try again to make sure */
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chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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for (i = 0; i < 8; i++)
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id_data[i] = chip->read_byte(mtd);
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if (id_data[0] != mfg_id || id_data[1] != dev_id) {
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printf("second ID read did not match");
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return -1;
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}
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debug("0x%02x:0x%02x ", mfg_id, dev_id);
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/* read ONFI */
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chip->onfi_version = 0;
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chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
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if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
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chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') {
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return -2;
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}
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/* we have ONFI, probe it */
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chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
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chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
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mtd->name = p->model;
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mtd->writesize = le32_to_cpu(p->byte_per_page);
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mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
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mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
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chip->chipsize = le32_to_cpu(p->blocks_per_lun);
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chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
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/* Calculate the address shift from the page size */
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chip->page_shift = ffs(mtd->writesize) - 1;
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chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
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/* Convert chipsize to number of pages per chip -1 */
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chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
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chip->badblockbits = 8;
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debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift);
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debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift);
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debug("oobsize=%d\n", mtd->oobsize);
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debug("chipsize=%lld\n", chip->chipsize);
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return 0;
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}
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static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
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{
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register struct nand_chip *chip = mtd_to_nand(mtd);
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int ret;
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chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
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ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page);
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if (ret < 0) {
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printf("read_page failed %d\n", ret);
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return -1;
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}
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return 0;
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}
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static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt)
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{
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register struct nand_chip *chip = mtd_to_nand(mtd);
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unsigned int block = offs >> chip->phys_erase_shift;
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unsigned int page = offs >> chip->page_shift;
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debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block,
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page);
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chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
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memset(chip->oob_poi, 0, mtd->oobsize);
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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return chip->oob_poi[0] != 0xff;
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}
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/* setup mtd and nand structs and init mxs_nand driver */
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static int mxs_nand_init(void)
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{
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/* return if already initalized */
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if (nand_chip.numchips)
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return 0;
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/* init mxs nand driver */
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board_nand_init(&nand_chip);
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mtd = nand_to_mtd(&nand_chip);
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/* set mtd functions */
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nand_chip.cmdfunc = mxs_nand_command;
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nand_chip.numchips = 1;
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/* identify flash device */
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if (mxs_flash_ident(mtd)) {
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printf("Failed to identify\n");
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return -1;
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}
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/* allocate and initialize buffers */
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nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
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sizeof(*nand_chip.buffers));
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nand_chip.oob_poi = nand_chip.buffers->databuf + mtd->writesize;
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/* setup flash layout (does not scan as we override that) */
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mtd->size = nand_chip.chipsize;
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nand_chip.scan_bbt(mtd);
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return 0;
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}
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
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{
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struct nand_chip *chip;
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unsigned int page;
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unsigned int nand_page_per_block;
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unsigned int sz = 0;
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if (mxs_nand_init())
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return -ENODEV;
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chip = mtd_to_nand(mtd);
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page = offs >> chip->page_shift;
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nand_page_per_block = mtd->erasesize / mtd->writesize;
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debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
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size = roundup(size, mtd->writesize);
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while (sz < size) {
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if (mxs_read_page_ecc(mtd, buf, page) < 0)
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return -1;
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sz += mtd->writesize;
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offs += mtd->writesize;
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page++;
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buf += mtd->writesize;
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/*
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* Check if we have crossed a block boundary, and if so
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* check for bad block.
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*/
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if (!(page % nand_page_per_block)) {
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/*
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* Yes, new block. See if this block is good. If not,
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* loop until we find a good block.
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*/
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while (is_badblock(mtd, offs, 1)) {
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page = page + nand_page_per_block;
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/* Check i we've reached the end of flash. */
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if (page >= mtd->size >> chip->page_shift)
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return -ENOMEM;
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}
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}
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}
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return 0;
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}
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int nand_default_bbt(struct mtd_info *mtd)
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{
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return 0;
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}
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void nand_init(void)
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{
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}
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void nand_deselect(void)
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{
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}
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