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This header was renamed to rawnand.h in Linux. The following is the corresponding commit in Linux. commit d4092d76a4a4e57b65910899948a83cc8646c5a5 Author: Boris Brezillon <boris.brezillon@free-electrons.com> Date: Fri Aug 4 17:29:10 2017 +0200 mtd: nand: Rename nand.h into rawnand.h We are planning to share more code between different NAND based devices (SPI NAND, OneNAND and raw NANDs), but before doing that we need to move the existing include/linux/mtd/nand.h file into include/linux/mtd/rawnand.h so we can later create a nand.h header containing all common structure and function prototypes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
812 lines
22 KiB
C
812 lines
22 KiB
C
/* Freescale Enhanced Local Bus Controller FCM NAND driver
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*
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* Copyright (c) 2006-2008 Freescale Semiconductor
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*
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* Authors: Nick Spence <nick.spence@freescale.com>,
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* Scott Wood <scottwood@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#ifdef VERBOSE_DEBUG
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#define DEBUG_ELBC
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#define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
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#else
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#define vdbg(format, arg...) do {} while (0)
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#endif
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/* Can't use plain old DEBUG because the linux mtd
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* headers define it as a macro.
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*/
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#ifdef DEBUG_ELBC
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#define dbg(format, arg...) printf("DEBUG: " format, ##arg)
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#else
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#define dbg(format, arg...) do {} while (0)
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#endif
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#define MAX_BANKS 8
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#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
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#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
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struct fsl_elbc_ctrl;
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/* mtd information per set */
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struct fsl_elbc_mtd {
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struct nand_chip chip;
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struct fsl_elbc_ctrl *ctrl;
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struct device *dev;
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int bank; /* Chip select bank number */
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u8 __iomem *vbase; /* Chip select base virtual address */
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int page_size; /* NAND page size (0=512, 1=2048) */
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unsigned int fmr; /* FCM Flash Mode Register value */
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};
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/* overview of the fsl elbc controller */
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struct fsl_elbc_ctrl {
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struct nand_hw_control controller;
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struct fsl_elbc_mtd *chips[MAX_BANKS];
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/* device info */
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fsl_lbc_t *regs;
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u8 __iomem *addr; /* Address of assigned FCM buffer */
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unsigned int page; /* Last page written to / read from */
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unsigned int read_bytes; /* Number of bytes read during command */
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unsigned int column; /* Saved column from SEQIN */
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unsigned int index; /* Pointer to next byte to 'read' */
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unsigned int status; /* status read from LTESR after last op */
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unsigned int mdr; /* UPM/FCM Data Register value */
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unsigned int use_mdr; /* Non zero if the MDR is to be set */
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unsigned int oob; /* Non zero if operating on OOB data */
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};
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/* These map to the positions used by the FCM hardware ECC generator */
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/* Small Page FLASH with FMR[ECCM] = 0 */
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static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
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.eccbytes = 3,
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.eccpos = {6, 7, 8},
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.oobfree = { {0, 5}, {9, 7} },
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};
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/* Small Page FLASH with FMR[ECCM] = 1 */
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static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
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.eccbytes = 3,
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.eccpos = {8, 9, 10},
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.oobfree = { {0, 5}, {6, 2}, {11, 5} },
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};
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/* Large Page FLASH with FMR[ECCM] = 0 */
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static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
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.eccbytes = 12,
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.eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
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.oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
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};
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/* Large Page FLASH with FMR[ECCM] = 1 */
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static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
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.eccbytes = 12,
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.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
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.oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
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};
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/*
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* fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
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* 1, so we have to adjust bad block pattern. This pattern should be used for
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* x8 chips only. So far hardware does not support x16 chips anyway.
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*/
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static u8 scan_ff_pattern[] = { 0xff, };
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static struct nand_bbt_descr largepage_memorybased = {
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.options = 0,
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.offs = 0,
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.len = 1,
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.pattern = scan_ff_pattern,
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};
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/*
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* ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
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* interfere with ECC positions, that's why we implement our own descriptors.
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* OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
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*/
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
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static struct nand_bbt_descr bbt_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = bbt_pattern,
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};
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static struct nand_bbt_descr bbt_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = mirror_pattern,
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};
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/*=================================*/
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/*
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* Set up the FCM hardware block and page address fields, and the fcm
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* structure addr field to point to the correct FCM buffer in memory
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*/
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static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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fsl_lbc_t *lbc = ctrl->regs;
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int buf_num;
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ctrl->page = page_addr;
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if (priv->page_size) {
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out_be32(&lbc->fbar, page_addr >> 6);
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out_be32(&lbc->fpar,
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((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
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(oob ? FPAR_LP_MS : 0) | column);
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buf_num = (page_addr & 1) << 2;
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} else {
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out_be32(&lbc->fbar, page_addr >> 5);
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out_be32(&lbc->fpar,
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((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
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(oob ? FPAR_SP_MS : 0) | column);
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buf_num = page_addr & 7;
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}
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ctrl->addr = priv->vbase + buf_num * 1024;
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ctrl->index = column;
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/* for OOB data point to the second half of the buffer */
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if (oob)
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ctrl->index += priv->page_size ? 2048 : 512;
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vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
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"index %x, pes %d ps %d\n",
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buf_num, ctrl->addr, priv->vbase, ctrl->index,
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chip->phys_erase_shift, chip->page_shift);
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}
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/*
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* execute FCM command and wait for it to complete
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*/
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static int fsl_elbc_run_command(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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fsl_lbc_t *lbc = ctrl->regs;
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u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
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u32 time_start;
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u32 ltesr;
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/* Setup the FMR[OP] to execute without write protection */
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out_be32(&lbc->fmr, priv->fmr | 3);
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if (ctrl->use_mdr)
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out_be32(&lbc->mdr, ctrl->mdr);
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vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
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in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
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vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
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"fbcr=%08x bank=%d\n",
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in_be32(&lbc->fbar), in_be32(&lbc->fpar),
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in_be32(&lbc->fbcr), priv->bank);
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/* execute special operation */
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out_be32(&lbc->lsor, priv->bank);
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/* wait for FCM complete flag or timeout */
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time_start = get_timer(0);
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ltesr = 0;
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while (get_timer(time_start) < timeo) {
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ltesr = in_be32(&lbc->ltesr);
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if (ltesr & LTESR_CC)
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break;
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}
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ctrl->status = ltesr & LTESR_NAND_MASK;
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out_be32(&lbc->ltesr, ctrl->status);
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out_be32(&lbc->lteatr, 0);
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/* store mdr value in case it was needed */
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if (ctrl->use_mdr)
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ctrl->mdr = in_be32(&lbc->mdr);
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ctrl->use_mdr = 0;
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vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
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ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
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/* returns 0 on success otherwise non-zero) */
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return ctrl->status == LTESR_CC ? 0 : -EIO;
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}
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static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
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{
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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fsl_lbc_t *lbc = ctrl->regs;
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if (priv->page_size) {
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out_be32(&lbc->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CA << FIR_OP1_SHIFT) |
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(FIR_OP_PA << FIR_OP2_SHIFT) |
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(FIR_OP_CW1 << FIR_OP3_SHIFT) |
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(FIR_OP_RBW << FIR_OP4_SHIFT));
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out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
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(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
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} else {
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out_be32(&lbc->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CA << FIR_OP1_SHIFT) |
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(FIR_OP_PA << FIR_OP2_SHIFT) |
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(FIR_OP_RBW << FIR_OP3_SHIFT));
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if (oob)
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out_be32(&lbc->fcr,
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NAND_CMD_READOOB << FCR_CMD0_SHIFT);
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else
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out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
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}
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}
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/* cmdfunc send commands to the FCM */
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static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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int column, int page_addr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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fsl_lbc_t *lbc = ctrl->regs;
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ctrl->use_mdr = 0;
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/* clear the read buffer */
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ctrl->read_bytes = 0;
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if (command != NAND_CMD_PAGEPROG)
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ctrl->index = 0;
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switch (command) {
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/* READ0 and READ1 read the entire buffer to use hardware ECC. */
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case NAND_CMD_READ1:
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column += 256;
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/* fall-through */
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case NAND_CMD_READ0:
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vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
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" 0x%x, column: 0x%x.\n", page_addr, column);
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out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
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set_addr(mtd, 0, page_addr, 0);
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ctrl->read_bytes = mtd->writesize + mtd->oobsize;
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ctrl->index += column;
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fsl_elbc_do_read(chip, 0);
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fsl_elbc_run_command(mtd);
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return;
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/* READOOB reads only the OOB because no ECC is performed. */
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case NAND_CMD_READOOB:
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vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
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" 0x%x, column: 0x%x.\n", page_addr, column);
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out_be32(&lbc->fbcr, mtd->oobsize - column);
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set_addr(mtd, column, page_addr, 1);
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ctrl->read_bytes = mtd->writesize + mtd->oobsize;
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fsl_elbc_do_read(chip, 1);
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fsl_elbc_run_command(mtd);
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return;
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/* READID must read all 5 possible bytes while CEB is active */
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case NAND_CMD_READID:
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case NAND_CMD_PARAM:
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vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
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out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_UA << FIR_OP1_SHIFT) |
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(FIR_OP_RBW << FIR_OP2_SHIFT));
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out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
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/*
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* although currently it's 8 bytes for READID, we always read
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* the maximum 256 bytes(for PARAM)
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*/
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out_be32(&lbc->fbcr, 256);
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ctrl->read_bytes = 256;
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ctrl->use_mdr = 1;
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ctrl->mdr = column;
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set_addr(mtd, 0, 0, 0);
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fsl_elbc_run_command(mtd);
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return;
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/* ERASE1 stores the block and page address */
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case NAND_CMD_ERASE1:
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vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
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"page_addr: 0x%x.\n", page_addr);
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set_addr(mtd, 0, page_addr, 0);
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return;
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/* ERASE2 uses the block and page address from ERASE1 */
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case NAND_CMD_ERASE2:
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vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
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out_be32(&lbc->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_PA << FIR_OP1_SHIFT) |
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(FIR_OP_CM1 << FIR_OP2_SHIFT));
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out_be32(&lbc->fcr,
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(NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
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(NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
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out_be32(&lbc->fbcr, 0);
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ctrl->read_bytes = 0;
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fsl_elbc_run_command(mtd);
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return;
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/* SEQIN sets up the addr buffer and all registers except the length */
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case NAND_CMD_SEQIN: {
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u32 fcr;
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vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
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"page_addr: 0x%x, column: 0x%x.\n",
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page_addr, column);
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ctrl->column = column;
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ctrl->oob = 0;
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if (priv->page_size) {
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fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
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(NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
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out_be32(&lbc->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CA << FIR_OP1_SHIFT) |
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(FIR_OP_PA << FIR_OP2_SHIFT) |
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(FIR_OP_WB << FIR_OP3_SHIFT) |
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(FIR_OP_CW1 << FIR_OP4_SHIFT));
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} else {
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fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
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(NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
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out_be32(&lbc->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CM2 << FIR_OP1_SHIFT) |
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(FIR_OP_CA << FIR_OP2_SHIFT) |
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(FIR_OP_PA << FIR_OP3_SHIFT) |
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(FIR_OP_WB << FIR_OP4_SHIFT) |
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(FIR_OP_CW1 << FIR_OP5_SHIFT));
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if (column >= mtd->writesize) {
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/* OOB area --> READOOB */
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column -= mtd->writesize;
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fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
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ctrl->oob = 1;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
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} else {
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/* Second 256 bytes --> READ1 */
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fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
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}
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}
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out_be32(&lbc->fcr, fcr);
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set_addr(mtd, column, page_addr, ctrl->oob);
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return;
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}
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/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
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case NAND_CMD_PAGEPROG: {
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vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
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"writing %d bytes.\n", ctrl->index);
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/* if the write did not start at 0 or is not a full page
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* then set the exact length, otherwise use a full page
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* write so the HW generates the ECC.
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*/
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if (ctrl->oob || ctrl->column != 0 ||
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ctrl->index != mtd->writesize + mtd->oobsize)
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out_be32(&lbc->fbcr, ctrl->index);
|
|
else
|
|
out_be32(&lbc->fbcr, 0);
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
return;
|
|
}
|
|
|
|
/* CMD_STATUS must read the status byte while CEB is active */
|
|
/* Note - it does not wait for the ready line */
|
|
case NAND_CMD_STATUS:
|
|
out_be32(&lbc->fir,
|
|
(FIR_OP_CM0 << FIR_OP0_SHIFT) |
|
|
(FIR_OP_RBW << FIR_OP1_SHIFT));
|
|
out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
|
|
out_be32(&lbc->fbcr, 1);
|
|
set_addr(mtd, 0, 0, 0);
|
|
ctrl->read_bytes = 1;
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
/* The chip always seems to report that it is
|
|
* write-protected, even when it is not.
|
|
*/
|
|
out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
|
|
return;
|
|
|
|
/* RESET without waiting for the ready line */
|
|
case NAND_CMD_RESET:
|
|
dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
|
|
out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
|
|
out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
|
|
fsl_elbc_run_command(mtd);
|
|
return;
|
|
|
|
default:
|
|
printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
|
|
command);
|
|
}
|
|
}
|
|
|
|
static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
|
|
{
|
|
/* The hardware does not seem to support multiple
|
|
* chips per bank.
|
|
*/
|
|
}
|
|
|
|
/*
|
|
* Write buf to the FCM Controller Data Buffer
|
|
*/
|
|
static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
|
|
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
|
|
unsigned int bufsize = mtd->writesize + mtd->oobsize;
|
|
|
|
if (len <= 0) {
|
|
printf("write_buf of %d bytes", len);
|
|
ctrl->status = 0;
|
|
return;
|
|
}
|
|
|
|
if ((unsigned int)len > bufsize - ctrl->index) {
|
|
printf("write_buf beyond end of buffer "
|
|
"(%d requested, %u available)\n",
|
|
len, bufsize - ctrl->index);
|
|
len = bufsize - ctrl->index;
|
|
}
|
|
|
|
memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
|
|
/*
|
|
* This is workaround for the weird elbc hangs during nand write,
|
|
* Scott Wood says: "...perhaps difference in how long it takes a
|
|
* write to make it through the localbus compared to a write to IMMR
|
|
* is causing problems, and sync isn't helping for some reason."
|
|
* Reading back the last byte helps though.
|
|
*/
|
|
in_8(&ctrl->addr[ctrl->index] + len - 1);
|
|
|
|
ctrl->index += len;
|
|
}
|
|
|
|
/*
|
|
* read a byte from either the FCM hardware buffer if it has any data left
|
|
* otherwise issue a command to read a single byte.
|
|
*/
|
|
static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
|
|
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
|
|
|
|
/* If there are still bytes in the FCM, then use the next byte. */
|
|
if (ctrl->index < ctrl->read_bytes)
|
|
return in_8(&ctrl->addr[ctrl->index++]);
|
|
|
|
printf("read_byte beyond end of buffer\n");
|
|
return ERR_BYTE;
|
|
}
|
|
|
|
/*
|
|
* Read from the FCM Controller Data Buffer
|
|
*/
|
|
static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
|
|
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
|
|
int avail;
|
|
|
|
if (len < 0)
|
|
return;
|
|
|
|
avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
|
|
memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
|
|
ctrl->index += avail;
|
|
|
|
if (len > avail)
|
|
printf("read_buf beyond end of buffer "
|
|
"(%d requested, %d available)\n",
|
|
len, avail);
|
|
}
|
|
|
|
/* This function is called after Program and Erase Operations to
|
|
* check for success or failure.
|
|
*/
|
|
static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
|
{
|
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
|
|
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
|
|
fsl_lbc_t *lbc = ctrl->regs;
|
|
|
|
if (ctrl->status != LTESR_CC)
|
|
return NAND_STATUS_FAIL;
|
|
|
|
/* Use READ_STATUS command, but wait for the device to be ready */
|
|
ctrl->use_mdr = 0;
|
|
out_be32(&lbc->fir,
|
|
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
|
|
(FIR_OP_RBW << FIR_OP1_SHIFT));
|
|
out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
|
|
out_be32(&lbc->fbcr, 1);
|
|
set_addr(mtd, 0, 0, 0);
|
|
ctrl->read_bytes = 1;
|
|
|
|
fsl_elbc_run_command(mtd);
|
|
|
|
if (ctrl->status != LTESR_CC)
|
|
return NAND_STATUS_FAIL;
|
|
|
|
/* The chip always seems to report that it is
|
|
* write-protected, even when it is not.
|
|
*/
|
|
out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
|
|
return fsl_elbc_read_byte(mtd);
|
|
}
|
|
|
|
static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
uint8_t *buf, int oob_required, int page)
|
|
{
|
|
fsl_elbc_read_buf(mtd, buf, mtd->writesize);
|
|
fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
|
|
mtd->ecc_stats.failed++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* ECC will be calculated automatically, and errors will be detected in
|
|
* waitfunc.
|
|
*/
|
|
static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
const uint8_t *buf, int oob_required,
|
|
int page)
|
|
{
|
|
fsl_elbc_write_buf(mtd, buf, mtd->writesize);
|
|
fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct fsl_elbc_ctrl *elbc_ctrl;
|
|
|
|
/* ECC will be calculated automatically, and errors will be detected in
|
|
* waitfunc.
|
|
*/
|
|
static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
|
|
uint32_t offset, uint32_t data_len,
|
|
const uint8_t *buf, int oob_required, int page)
|
|
{
|
|
fsl_elbc_write_buf(mtd, buf, mtd->writesize);
|
|
fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void fsl_elbc_ctrl_init(void)
|
|
{
|
|
elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
|
|
if (!elbc_ctrl)
|
|
return;
|
|
|
|
elbc_ctrl->regs = LBC_BASE_ADDR;
|
|
|
|
/* clear event registers */
|
|
out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
|
|
out_be32(&elbc_ctrl->regs->lteatr, 0);
|
|
|
|
/* Enable interrupts for any detected events */
|
|
out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
|
|
|
|
elbc_ctrl->read_bytes = 0;
|
|
elbc_ctrl->index = 0;
|
|
elbc_ctrl->addr = NULL;
|
|
}
|
|
|
|
static int fsl_elbc_chip_init(int devnum, u8 *addr)
|
|
{
|
|
struct mtd_info *mtd;
|
|
struct nand_chip *nand;
|
|
struct fsl_elbc_mtd *priv;
|
|
uint32_t br = 0, or = 0;
|
|
int ret;
|
|
|
|
if (!elbc_ctrl) {
|
|
fsl_elbc_ctrl_init();
|
|
if (!elbc_ctrl)
|
|
return -1;
|
|
}
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->ctrl = elbc_ctrl;
|
|
priv->vbase = addr;
|
|
|
|
/* Find which chip select it is connected to. It'd be nice
|
|
* if we could pass more than one datum to the NAND driver...
|
|
*/
|
|
for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
|
|
phys_addr_t phys_addr = virt_to_phys(addr);
|
|
|
|
br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
|
|
or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
|
|
|
|
if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
|
|
(br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
|
|
break;
|
|
}
|
|
|
|
if (priv->bank >= MAX_BANKS) {
|
|
printf("fsl_elbc_nand: address did not match any "
|
|
"chip selects\n");
|
|
kfree(priv);
|
|
return -ENODEV;
|
|
}
|
|
|
|
nand = &priv->chip;
|
|
mtd = nand_to_mtd(nand);
|
|
|
|
elbc_ctrl->chips[priv->bank] = priv;
|
|
|
|
/* fill in nand_chip structure */
|
|
/* set up function call table */
|
|
nand->read_byte = fsl_elbc_read_byte;
|
|
nand->write_buf = fsl_elbc_write_buf;
|
|
nand->read_buf = fsl_elbc_read_buf;
|
|
nand->select_chip = fsl_elbc_select_chip;
|
|
nand->cmdfunc = fsl_elbc_cmdfunc;
|
|
nand->waitfunc = fsl_elbc_wait;
|
|
|
|
/* set up nand options */
|
|
nand->bbt_td = &bbt_main_descr;
|
|
nand->bbt_md = &bbt_mirror_descr;
|
|
|
|
/* set up nand options */
|
|
nand->options = NAND_NO_SUBPAGE_WRITE;
|
|
nand->bbt_options = NAND_BBT_USE_FLASH;
|
|
|
|
nand->controller = &elbc_ctrl->controller;
|
|
nand_set_controller_data(nand, priv);
|
|
|
|
nand->ecc.read_page = fsl_elbc_read_page;
|
|
nand->ecc.write_page = fsl_elbc_write_page;
|
|
nand->ecc.write_subpage = fsl_elbc_write_subpage;
|
|
|
|
priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
|
|
|
|
/* If CS Base Register selects full hardware ECC then use it */
|
|
if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
|
|
nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
|
|
&fsl_elbc_oob_sp_eccm1 :
|
|
&fsl_elbc_oob_sp_eccm0;
|
|
|
|
nand->ecc.size = 512;
|
|
nand->ecc.bytes = 3;
|
|
nand->ecc.steps = 1;
|
|
nand->ecc.strength = 1;
|
|
} else {
|
|
/* otherwise fall back to software ECC */
|
|
#if defined(CONFIG_NAND_ECC_BCH)
|
|
nand->ecc.mode = NAND_ECC_SOFT_BCH;
|
|
#else
|
|
nand->ecc.mode = NAND_ECC_SOFT;
|
|
#endif
|
|
}
|
|
|
|
ret = nand_scan_ident(mtd, 1, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Large-page-specific setup */
|
|
if (mtd->writesize == 2048) {
|
|
setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
|
|
OR_FCM_PGS);
|
|
in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
|
|
|
|
priv->page_size = 1;
|
|
nand->badblock_pattern = &largepage_memorybased;
|
|
|
|
/*
|
|
* Hardware expects small page has ECCM0, large page has
|
|
* ECCM1 when booting from NAND, and we follow that even
|
|
* when not booting from NAND.
|
|
*/
|
|
priv->fmr |= FMR_ECCM;
|
|
|
|
/* adjust ecc setup if needed */
|
|
if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
|
|
nand->ecc.steps = 4;
|
|
nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
|
|
&fsl_elbc_oob_lp_eccm1 :
|
|
&fsl_elbc_oob_lp_eccm0;
|
|
}
|
|
} else if (mtd->writesize == 512) {
|
|
clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
|
|
OR_FCM_PGS);
|
|
in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
|
|
} else {
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = nand_scan_tail(mtd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nand_register(devnum, mtd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifndef CONFIG_SYS_NAND_BASE_LIST
|
|
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
|
#endif
|
|
|
|
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
|
|
CONFIG_SYS_NAND_BASE_LIST;
|
|
|
|
void board_nand_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
|
|
fsl_elbc_chip_init(i, (u8 *)base_address[i]);
|
|
}
|