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https://github.com/brain-hackers/u-boot-brain
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4a41a1a6f0
We will generate DRAM 4000MT/s as default for i.MX8MP. So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller. Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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.. | ||
ddr_init.c | ||
ddrphy_csr.c | ||
ddrphy_train.c | ||
ddrphy_utils.c | ||
helper.c | ||
Kconfig | ||
Makefile |