Daniel Schwierzeck bd60252811 MIPS: reserve space for exception vectors ... In order to set own exception handlers, a table with the exception vectors must be built in DRAM and the CPU EBase register must be set to the base address of this table. Reserve the space above the stack and use gd->irq_sp as storage for the exception base address. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>		2016-11-30 16:11:46 +01:00
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cpu	MIPS: add possibility to setup initial stack and global data in SRAM	2016-11-30 16:11:46 +01:00
dts	boston: Introduce support for the MIPS Boston development board	2016-09-21 16:24:36 +02:00
include/asm	MIPS: add asm-offsets for struct pt_regs	2016-11-30 16:11:46 +01:00
lib	MIPS: reserve space for exception vectors	2016-11-30 16:11:46 +01:00
mach-ath79	MIPS: make inclusion of ROM exception vectors configurable	2016-11-30 16:07:17 +01:00
mach-au1x00	Fix spelling of "resetting".	2016-10-31 10:13:17 -04:00
mach-pic32	MIPS: make inclusion of ROM exception vectors configurable	2016-11-30 16:07:17 +01:00
config.mk	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
Kconfig	MIPS: add possibility to setup initial stack and global data in SRAM	2016-11-30 16:11:46 +01:00
Makefile	MIPS: add tune for MIPS 34kc	2016-05-31 09:38:11 +02:00