mirror of
https://github.com/brain-hackers/u-boot-brain
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217 lines
5.3 KiB
C
217 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Google, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <pch.h>
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#include <pci.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GPIO_USESEL_OFFSET(x) (x)
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#define GPIO_IOSEL_OFFSET(x) (x + 4)
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#define GPIO_LVL_OFFSET(x) ((x) ? (x) + 8 : 0xc)
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#define GPI_INV 0x2c
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#define IOPAD_MODE_MASK 0x7
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#define IOPAD_PULL_ASSIGN_SHIFT 7
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#define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
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#define IOPAD_PULL_STRENGTH_SHIFT 9
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#define IOPAD_PULL_STRENGTH_MASK (0x3 << IOPAD_PULL_STRENGTH_SHIFT)
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static int ich6_pinctrl_set_value(uint16_t base, unsigned offset, int value)
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{
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if (value)
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setio_32(base, 1UL << offset);
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else
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clrio_32(base, 1UL << offset);
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return 0;
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}
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static int ich6_pinctrl_set_function(uint16_t base, unsigned offset, int func)
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{
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if (func)
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setio_32(base, 1UL << offset);
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else
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clrio_32(base, 1UL << offset);
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return 0;
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}
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static int ich6_pinctrl_set_direction(uint16_t base, unsigned offset, int dir)
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{
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if (!dir)
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setio_32(base, 1UL << offset);
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else
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clrio_32(base, 1UL << offset);
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return 0;
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}
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static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
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{
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bool is_gpio, invert;
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u32 gpio_offset[2];
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int pad_offset;
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int dir, val;
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int ret;
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/*
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* GPIO node is not mandatory, so we only do the pinmuxing if the
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* node exists.
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*/
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ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
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gpio_offset, 2);
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if (!ret) {
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/* Do we want to force the GPIO mode? */
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is_gpio = fdtdec_get_bool(gd->fdt_blob, pin_node, "mode-gpio");
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if (is_gpio)
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ich6_pinctrl_set_function(GPIO_USESEL_OFFSET(gpiobase) +
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gpio_offset[0], gpio_offset[1],
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1);
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dir = fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
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if (dir != -1)
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ich6_pinctrl_set_direction(GPIO_IOSEL_OFFSET(gpiobase) +
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gpio_offset[0], gpio_offset[1],
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dir);
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val = fdtdec_get_int(gd->fdt_blob, pin_node, "output-value",
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-1);
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if (val != -1)
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ich6_pinctrl_set_value(GPIO_LVL_OFFSET(gpiobase) +
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gpio_offset[0], gpio_offset[1],
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val);
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invert = fdtdec_get_bool(gd->fdt_blob, pin_node, "invert");
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if (invert)
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setio_32(gpiobase + GPI_INV, 1 << gpio_offset[1]);
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debug("gpio %#x bit %d, is_gpio %d, dir %d, val %d, invert %d\n",
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gpio_offset[0], gpio_offset[1], is_gpio, dir, val,
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invert);
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}
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/* if iobase is present, let's configure the pad */
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if (iobase != -1) {
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ulong iobase_addr;
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/*
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* The offset for the same pin for the IOBASE and GPIOBASE are
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* different, so instead of maintaining a lookup table,
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* the device tree should provide directly the correct
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* value for both mapping.
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*/
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pad_offset = fdtdec_get_int(gd->fdt_blob, pin_node,
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"pad-offset", -1);
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if (pad_offset == -1)
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return 0;
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/* compute the absolute pad address */
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iobase_addr = iobase + pad_offset;
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/*
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* Do we need to set a specific function mode?
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* If someone put also 'mode-gpio', this option will
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* be just ignored by the controller
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*/
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val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
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if (val != -1)
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clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
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/* Configure the pull-up/down if needed */
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val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
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if (val != -1)
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clrsetbits_le32(iobase_addr,
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IOPAD_PULL_ASSIGN_MASK,
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val << IOPAD_PULL_ASSIGN_SHIFT);
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val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength",
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-1);
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if (val != -1)
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clrsetbits_le32(iobase_addr,
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IOPAD_PULL_STRENGTH_MASK,
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val << IOPAD_PULL_STRENGTH_SHIFT);
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debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
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readl(iobase_addr));
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}
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return 0;
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}
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static int ich6_pinctrl_probe(struct udevice *dev)
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{
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struct udevice *pch;
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int pin_node;
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int ret;
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u32 gpiobase;
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u32 iobase = -1;
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debug("%s: start\n", __func__);
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ret = uclass_first_device(UCLASS_PCH, &pch);
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if (ret)
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return ret;
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if (!pch)
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return -ENODEV;
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/*
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* Get the memory/io base address to configure every pins.
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* IOBASE is used to configure the mode/pads
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* GPIOBASE is used to configure the direction and default value
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*/
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ret = pch_get_gpio_base(pch, &gpiobase);
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if (ret) {
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debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
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gpiobase);
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return -EINVAL;
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}
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/*
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* Get the IOBASE, this is not mandatory as this is not
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* supported by all the CPU
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*/
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ret = pch_get_io_base(pch, &iobase);
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if (ret && ret != -ENOSYS) {
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debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase);
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return -EINVAL;
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}
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for (pin_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
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pin_node > 0;
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pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
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/* Configure the pin */
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ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
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if (ret != 0) {
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debug("%s: invalid configuration for the pin %d\n",
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__func__, pin_node);
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return ret;
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}
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}
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debug("%s: done\n", __func__);
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return 0;
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}
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static const struct udevice_id ich6_pinctrl_match[] = {
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{ .compatible = "intel,x86-pinctrl", .data = X86_SYSCON_PINCONF },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(ich6_pinctrl) = {
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.name = "ich6_pinctrl",
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.id = UCLASS_SYSCON,
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.of_match = ich6_pinctrl_match,
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.probe = ich6_pinctrl_probe,
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};
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