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![Simon Glass](/assets/img/avatar_default.png)
The change to avoid searching the device tree does not work on boards
wich don't have driver model set up this early, for example minnowmax.
Put back the old code (converted to livetree) as a fallback for these
devices. Also update the documentation.
This is tested on minnowmax, link, samus and coral.
Fixes: 87f1084a63
(x86: Adjust mrccache_get_region() to use livetree)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)
357 lines
8.8 KiB
C
357 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* From coreboot src/southbridge/intel/bd82x6x/mrccache.c
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <malloc.h>
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#include <net.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <asm/mrccache.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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static uint mrc_block_size(uint data_size)
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{
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uint mrc_size = sizeof(struct mrc_data_container) + data_size;
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return ALIGN(mrc_size, MRC_DATA_ALIGN);
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}
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static struct mrc_data_container *next_mrc_block(
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struct mrc_data_container *cache)
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{
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/* MRC data blocks are aligned within the region */
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u8 *region_ptr = (u8 *)cache;
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region_ptr += mrc_block_size(cache->data_size);
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return (struct mrc_data_container *)region_ptr;
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}
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static int is_mrc_cache(struct mrc_data_container *cache)
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{
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return cache && (cache->signature == MRC_DATA_SIGNATURE);
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}
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struct mrc_data_container *mrccache_find_current(struct mrc_region *entry)
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{
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struct mrc_data_container *cache, *next;
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ulong base_addr, end_addr;
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uint id;
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base_addr = entry->base + entry->offset;
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end_addr = base_addr + entry->length;
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cache = NULL;
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/* Search for the last filled entry in the region */
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for (id = 0, next = (struct mrc_data_container *)base_addr;
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is_mrc_cache(next);
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id++) {
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cache = next;
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next = next_mrc_block(next);
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if ((ulong)next >= end_addr)
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break;
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}
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if (id-- == 0) {
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debug("%s: No valid MRC cache found.\n", __func__);
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return NULL;
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}
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/* Verify checksum */
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if (cache->checksum != compute_ip_checksum(cache->data,
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cache->data_size)) {
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printf("%s: MRC cache checksum mismatch\n", __func__);
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return NULL;
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}
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debug("%s: picked entry %u from cache block\n", __func__, id);
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return cache;
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}
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/**
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* find_next_mrc_cache() - get next cache entry
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*
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* This moves to the next cache entry in the region, making sure it has enough
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* space to hold data of size @data_size.
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*
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* @entry: MRC cache flash area
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* @cache: Entry to start from
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* @data_size: Required data size of the new entry. Note that we assume that
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* all cache entries are the same size
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*
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* @return next cache entry if found, NULL if we got to the end
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*/
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static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
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struct mrc_data_container *prev, int data_size)
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{
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struct mrc_data_container *cache;
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ulong base_addr, end_addr;
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base_addr = entry->base + entry->offset;
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end_addr = base_addr + entry->length;
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/*
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* We assume that all cache entries are the same size, but let's use
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* data_size here for clarity.
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*/
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cache = next_mrc_block(prev);
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if ((ulong)cache + mrc_block_size(data_size) > end_addr) {
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/* Crossed the boundary */
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cache = NULL;
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debug("%s: no available entries found\n", __func__);
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} else {
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debug("%s: picked next entry from cache block at %p\n",
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__func__, cache);
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}
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return cache;
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}
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/**
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* mrccache_update() - update the MRC cache with a new record
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*
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* This writes a new record to the end of the MRC cache region. If the new
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* record is the same as the latest record then the write is skipped
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*
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* @sf: SPI flash to write to
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* @entry: Position and size of MRC cache in SPI flash
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* @cur: Record to write
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* @return 0 if updated, -EEXIST if the record is the same as the latest
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* record, -EINVAL if the record is not valid, other error if SPI write failed
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*/
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static int mrccache_update(struct udevice *sf, struct mrc_region *entry,
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struct mrc_data_container *cur)
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{
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struct mrc_data_container *cache;
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ulong offset;
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ulong base_addr;
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int ret;
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if (!is_mrc_cache(cur)) {
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debug("%s: Cache data not valid\n", __func__);
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return -EINVAL;
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}
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/* Find the last used block */
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base_addr = entry->base + entry->offset;
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debug("Updating MRC cache data\n");
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cache = mrccache_find_current(entry);
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if (cache && (cache->data_size == cur->data_size) &&
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(!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) {
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debug("MRC data in flash is up to date. No update\n");
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return -EEXIST;
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}
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/* Move to the next block, which will be the first unused block */
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if (cache)
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cache = find_next_mrc_cache(entry, cache, cur->data_size);
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/*
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* If we have got to the end, erase the entire mrc-cache area and start
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* again at block 0.
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*/
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if (!cache) {
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debug("Erasing the MRC cache region of %x bytes at %x\n",
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entry->length, entry->offset);
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ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
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if (ret) {
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debug("Failed to erase flash region\n");
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return ret;
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}
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cache = (struct mrc_data_container *)base_addr;
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}
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/* Write the data out */
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offset = (ulong)cache - base_addr + entry->offset;
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debug("Write MRC cache update to flash at %lx\n", offset);
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ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
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cur);
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if (ret) {
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debug("Failed to write to SPI flash\n");
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return log_msg_ret("Cannot update mrccache", ret);
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}
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return 0;
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}
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static void mrccache_setup(struct mrc_output *mrc, void *data)
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{
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struct mrc_data_container *cache = data;
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u16 checksum;
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cache->signature = MRC_DATA_SIGNATURE;
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cache->data_size = mrc->len;
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checksum = compute_ip_checksum(mrc->buf, cache->data_size);
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debug("Saving %d bytes for MRC output data, checksum %04x\n",
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cache->data_size, checksum);
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cache->checksum = checksum;
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cache->reserved = 0;
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memcpy(cache->data, mrc->buf, cache->data_size);
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mrc->cache = cache;
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}
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int mrccache_reserve(void)
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{
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int i;
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for (i = 0; i < MRC_TYPE_COUNT; i++) {
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struct mrc_output *mrc = &gd->arch.mrc[i];
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if (!mrc->len)
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continue;
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/* adjust stack pointer to store pure cache data plus header */
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gd->start_addr_sp -= (mrc->len + MRC_DATA_HEADER_SIZE);
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mrccache_setup(mrc, (void *)gd->start_addr_sp);
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gd->start_addr_sp &= ~0xf;
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}
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return 0;
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}
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int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
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struct mrc_region *entry)
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{
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struct udevice *dev;
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ofnode mrc_node;
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ulong map_base;
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uint map_size;
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uint offset;
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ofnode node;
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u32 reg[2];
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int ret;
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/*
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* Find the flash chip within the SPI controller node. Avoid probing
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* the device here since it may put it into a strange state where the
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* memory map cannot be read.
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*/
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ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
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if (ret || !dev) {
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/*
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* Fall back to searching the device tree since driver model
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* may not be ready yet (e.g. with FSPv1)
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*/
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node = ofnode_by_compatible(ofnode_null(), "jedec,spi-nor");
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if (!ofnode_valid(node))
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return log_msg_ret("Cannot find SPI flash\n", -ENOENT);
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ret = -ENODEV;
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} else {
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ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
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if (!ret)
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entry->base = map_base;
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node = dev_ofnode(dev);
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}
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/*
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* At this point we have entry->base if ret == 0. If not, then we have
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* the node and can look for memory-map
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*/
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if (ret) {
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ret = ofnode_read_u32_array(node, "memory-map", reg, 2);
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if (ret)
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return log_msg_ret("Cannot find memory map\n", ret);
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entry->base = reg[0];
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}
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/* Find the place where we put the MRC cache */
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mrc_node = ofnode_find_subnode(node, type == MRC_TYPE_NORMAL ?
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"rw-mrc-cache" : "rw-var-mrc-cache");
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if (!ofnode_valid(mrc_node))
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return log_msg_ret("Cannot find node", -EPERM);
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ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2);
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if (ret)
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return log_msg_ret("Cannot find address", ret);
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entry->offset = reg[0];
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entry->length = reg[1];
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if (devp)
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*devp = dev;
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debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n",
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type, dev ? dev->name : ofnode_get_name(node), entry->offset,
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entry->length, entry->base);
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return 0;
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}
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static int mrccache_save_type(enum mrc_type_t type)
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{
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struct mrc_data_container *cache;
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struct mrc_output *mrc;
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struct mrc_region entry;
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struct udevice *sf;
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int ret;
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mrc = &gd->arch.mrc[type];
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if (!mrc->len)
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return 0;
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log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n",
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mrc->len, type);
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ret = mrccache_get_region(type, &sf, &entry);
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if (ret)
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return log_msg_ret("Cannot get region", ret);
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ret = device_probe(sf);
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if (ret)
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return log_msg_ret("Cannot probe device", ret);
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cache = mrc->cache;
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ret = mrccache_update(sf, &entry, cache);
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if (!ret)
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debug("Saved MRC data with checksum %04x\n", cache->checksum);
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else if (ret == -EEXIST)
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debug("MRC data is the same as last time, skipping save\n");
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return 0;
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}
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int mrccache_save(void)
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{
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int i;
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for (i = 0; i < MRC_TYPE_COUNT; i++) {
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int ret;
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ret = mrccache_save_type(i);
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if (ret)
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return ret;
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}
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return 0;
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}
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int mrccache_spl_save(void)
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{
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int i;
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for (i = 0; i < MRC_TYPE_COUNT; i++) {
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struct mrc_output *mrc = &gd->arch.mrc[i];
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void *data;
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int size;
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size = mrc->len + MRC_DATA_HEADER_SIZE;
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data = malloc(size);
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if (!data)
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return log_msg_ret("Allocate MRC cache block", -ENOMEM);
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mrccache_setup(mrc, data);
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}
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return mrccache_save();
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}
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