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https://github.com/brain-hackers/u-boot-brain
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5318f18d2c
Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
32 lines
1.2 KiB
Plaintext
32 lines
1.2 KiB
Plaintext
Intel x86 PINCTRL/GPIO controller
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Pin-muxing on x86 can be described with a node for the PINCTRL master
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node and a set of child nodes for each pin on the SoC.
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The PINCTRL master node requires the following properties:
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- compatible : "intel,x86-pinctrl"
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Pin nodes must be children of the pinctrl master node and can
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contain the following properties:
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- pad-offset - (required) offset in the IOBASE for the pin to configured.
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- gpio-offset - (required) offset in the GPIOBASE for the pin to configured and
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also the bit shift in this register.
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- mode-gpio - (optional) standalone property to force the pin into GPIO mode.
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- mode-func - (optional) function number to assign to the pin. if 'mode-gpio'
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is set, this property will be ignored.
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in case of 'mode-gpio' property set:
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- output-value - (optional) this set the default output value of the GPIO.
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- direction - (optional) this set the direction of the gpio.
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- pull-str - (optional) this set the pull strength of the pin.
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- pull-assign - (optional) this set the pull assignement (up/down) of the pin.
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Example:
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pin_usb_host_en0@0 {
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gpio-offset = <0x80 8>;
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pad-offset = <0x260>;
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mode-gpio;
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output-value = <1>;
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direction = <PIN_OUTPUT>;
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};
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