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https://github.com/brain-hackers/u-boot-brain
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9830d2ebb4
Turn on PCIe ECAM address range decoding on Q35. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <pci_rom.h>
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#include <asm/pci.h>
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#include <asm/arch/device.h>
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#include <asm/arch/qemu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static bool i440fx;
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_PREF_BUS,
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CONFIG_PCI_PREF_PHYS,
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CONFIG_PCI_PREF_SIZE,
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PCI_REGION_PREFETCH);
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pci_set_region(hose->regions + 3,
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0,
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0,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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}
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int board_pci_post_scan(struct pci_controller *hose)
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{
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int ret = 0;
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u16 device, xbcs;
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int pam, i;
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pci_dev_t vga;
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ulong start;
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/*
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* i440FX and Q35 chipset have different PAM register offset, but with
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* the same bitfield layout. Here we determine the offset based on its
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* PCI device ID.
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*/
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device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
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i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
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pam = i440fx ? I440FX_PAM : Q35_PAM;
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/*
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* Initialize Programmable Attribute Map (PAM) Registers
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*
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* Configure legacy segments C/D/E/F to system RAM
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*/
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for (i = 0; i < PAM_NUM; i++)
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x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
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if (i440fx) {
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/*
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* Enable legacy IDE I/O ports decode
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*
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* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
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* However Linux ata_piix driver does sanity check on these two
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* registers to see whether legacy ports decode is turned on.
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* This is to make Linux ata_piix driver happy.
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*/
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x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
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x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
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/* Enable I/O APIC */
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xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
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xbcs |= APIC_EN;
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x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
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} else {
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/* Configure PCIe ECAM base address */
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x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
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CONFIG_PCIE_ECAM_BASE | BAR_EN);
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}
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/*
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* QEMU emulated graphic card shows in the PCI configuration space with
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* PCI vendor id and device id as an artificial pair 0x1234:0x1111.
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* It is on PCI bus 0, function 0, but device number is not consistent
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* for the two x86 targets it supports. For i440FX and PIIX chipset
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* board, it shows as device 2, while for Q35 and ICH9 chipset board,
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* it shows as device 1.
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*/
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vga = i440fx ? I440FX_VGA : Q35_VGA;
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start = get_timer(0);
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ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE);
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debug("BIOS ran in %lums\n", get_timer(start));
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return ret;
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}
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#ifdef CONFIG_GENERATE_MP_TABLE
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int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
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{
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u8 irq;
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if (i440fx) {
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/*
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* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
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* connected to I/O APIC INTPIN#16-19. Instead they are routed
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* to an irq number controled by the PIRQ routing register.
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*/
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irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
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PCI_INTERRUPT_LINE);
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} else {
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/*
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* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
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* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
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*/
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irq = pirq < 8 ? pirq + 16 : pirq + 12;
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}
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return irq;
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}
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#endif
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