York Sun bcb6c2bb84 Enabled support for Rev 1.3 SPD for DDR2 DIMMs ... SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. The difference has ben examined and the code is compatible. Speed bins is not verified on hardware for CL7 at this moment. This patch also enables SPD Rev 1.x where x is up to "F". According to SPD spec, the lower nibble is optionally used to determine which additinal bytes or attribute bits have been defined. Software can safely use defaults. However, the upper nibble should always be checked. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2010-05-12 04:54:30 -05:00
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74xx_7xx	Move arch/ppc to arch/powerpc	2010-04-21 23:42:38 +02:00
mpc5xx	Move arch/ppc to arch/powerpc	2010-04-21 23:42:38 +02:00
mpc5xxx	powerpc: Consolidate bootcount_{store|load} for PowerPC	2010-05-06 23:28:48 +02:00
mpc8xx	powerpc: Consolidate bootcount_{store|load} for PowerPC	2010-05-06 23:28:48 +02:00
mpc8xxx	Enabled support for Rev 1.3 SPD for DDR2 DIMMs	2010-05-12 04:54:30 -05:00
mpc83xx	powerpc: Consolidate bootcount_{store|load} for PowerPC	2010-05-06 23:28:48 +02:00
mpc85xx	85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled	2010-05-12 04:53:51 -05:00
mpc86xx	Move arch/ppc to arch/powerpc	2010-04-21 23:42:38 +02:00
mpc512x	mpc5121: add common post_word_load/store code	2010-04-24 22:56:39 +02:00
mpc824x	Move arch/ppc to arch/powerpc	2010-04-21 23:42:38 +02:00
mpc8220	Remove unused "local_crc32" function.	2010-05-03 14:52:48 -07:00
mpc8260	powerpc: Consolidate bootcount_{store|load} for PowerPC	2010-05-06 23:28:48 +02:00
ppc4xx	powerpc: Consolidate bootcount_{store|load} for PowerPC	2010-05-06 23:28:48 +02:00