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![Siew Chin Lim](/assets/img/avatar_default.png)
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
9 lines
346 B
Plaintext
9 lines
346 B
Plaintext
config SPL_ALTERA_SDRAM
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bool "SoCFPGA DDR SDRAM driver in SPL"
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depends on SPL
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depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64
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select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
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select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
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help
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Enable DDR SDRAM controller for the SoCFPGA devices.
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