mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
330 lines
6.3 KiB
C
330 lines
6.3 KiB
C
/*
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* TI DaVinci (TMS320DM644x) I2C driver.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* --------------------------------------------------------
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/i2c_defs.h>
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#define CHECK_NACK() \
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do {\
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if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
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REG(I2C_CON) = 0;\
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return(1);\
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}\
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} while (0)
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static int wait_for_bus(void)
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{
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int stat, timeout;
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REG(I2C_STAT) = 0xffff;
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for (timeout = 0; timeout < 10; timeout++) {
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if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
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REG(I2C_STAT) = 0xffff;
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return(0);
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}
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REG(I2C_STAT) = stat;
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udelay(50000);
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}
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REG(I2C_STAT) = 0xffff;
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return(1);
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}
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static int poll_i2c_irq(int mask)
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{
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int stat, timeout;
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for (timeout = 0; timeout < 10; timeout++) {
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udelay(1000);
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stat = REG(I2C_STAT);
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if (stat & mask) {
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return(stat);
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}
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}
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REG(I2C_STAT) = 0xffff;
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return(stat | I2C_TIMEOUT);
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}
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void flush_rx(void)
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{
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int dummy;
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while (1) {
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if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
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break;
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dummy = REG(I2C_DRR);
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REG(I2C_STAT) = I2C_STAT_RRDY;
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udelay(1000);
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}
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}
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void i2c_init(int speed, int slaveadd)
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{
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u_int32_t div, psc;
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if (REG(I2C_CON) & I2C_CON_EN) {
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REG(I2C_CON) = 0;
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udelay (50000);
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}
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psc = 2;
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div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
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REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
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REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
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REG(I2C_SCLH) = div - REG(I2C_SCLL);
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REG(I2C_OA) = slaveadd;
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REG(I2C_CNT) = 0;
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/* Interrupts must be enabled or I2C module won't work */
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REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
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I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
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/* Now enable I2C controller (get it out of reset) */
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REG(I2C_CON) = I2C_CON_EN;
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udelay(1000);
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}
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int i2c_probe(u_int8_t chip)
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{
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int rc = 1;
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if (chip == REG(I2C_OA)) {
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return(rc);
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}
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REG(I2C_CON) = 0;
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if (wait_for_bus()) {return(1);}
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/* try to read one byte from current (or only) address */
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REG(I2C_CNT) = 1;
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REG(I2C_SA) = chip;
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REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
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udelay (50000);
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if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
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rc = 0;
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flush_rx();
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REG(I2C_STAT) = 0xffff;
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} else {
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REG(I2C_STAT) = 0xffff;
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REG(I2C_CON) |= I2C_CON_STP;
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udelay(20000);
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if (wait_for_bus()) {return(1);}
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}
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flush_rx();
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REG(I2C_STAT) = 0xffff;
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REG(I2C_CNT) = 0;
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return(rc);
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}
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int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
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{
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u_int32_t tmp;
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int i;
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if ((alen < 0) || (alen > 2)) {
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printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
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return(1);
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}
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if (wait_for_bus()) {return(1);}
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if (alen != 0) {
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/* Start address phase */
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tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
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REG(I2C_CNT) = alen;
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REG(I2C_SA) = chip;
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REG(I2C_CON) = tmp;
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tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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switch (alen) {
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case 2:
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/* Send address MSByte */
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if (tmp & I2C_STAT_XRDY) {
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REG(I2C_DXR) = (addr >> 8) & 0xff;
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} else {
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REG(I2C_CON) = 0;
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return(1);
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}
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tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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/* No break, fall through */
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case 1:
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/* Send address LSByte */
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if (tmp & I2C_STAT_XRDY) {
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REG(I2C_DXR) = addr & 0xff;
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} else {
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REG(I2C_CON) = 0;
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return(1);
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}
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tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
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CHECK_NACK();
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if (!(tmp & I2C_STAT_ARDY)) {
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REG(I2C_CON) = 0;
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return(1);
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}
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}
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}
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/* Address phase is over, now read 'len' bytes and stop */
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tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
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REG(I2C_CNT) = len & 0xffff;
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REG(I2C_SA) = chip;
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REG(I2C_CON) = tmp;
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for (i = 0; i < len; i++) {
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tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
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CHECK_NACK();
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if (tmp & I2C_STAT_RRDY) {
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buf[i] = REG(I2C_DRR);
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} else {
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REG(I2C_CON) = 0;
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return(1);
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}
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}
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tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
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CHECK_NACK();
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if (!(tmp & I2C_STAT_SCD)) {
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REG(I2C_CON) = 0;
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return(1);
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}
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flush_rx();
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REG(I2C_STAT) = 0xffff;
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REG(I2C_CNT) = 0;
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REG(I2C_CON) = 0;
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return(0);
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}
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int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
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{
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u_int32_t tmp;
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int i;
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if ((alen < 0) || (alen > 2)) {
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printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
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return(1);
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}
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if (len < 0) {
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printf("%s(): bogus length %x\n", __FUNCTION__, len);
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return(1);
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}
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if (wait_for_bus()) {return(1);}
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/* Start address phase */
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tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
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REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
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REG(I2C_SA) = chip;
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REG(I2C_CON) = tmp;
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switch (alen) {
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case 2:
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/* Send address MSByte */
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tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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if (tmp & I2C_STAT_XRDY) {
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REG(I2C_DXR) = (addr >> 8) & 0xff;
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} else {
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REG(I2C_CON) = 0;
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return(1);
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}
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/* No break, fall through */
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case 1:
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/* Send address LSByte */
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tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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if (tmp & I2C_STAT_XRDY) {
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REG(I2C_DXR) = addr & 0xff;
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} else {
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REG(I2C_CON) = 0;
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return(1);
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}
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}
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for (i = 0; i < len; i++) {
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tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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if (tmp & I2C_STAT_XRDY) {
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REG(I2C_DXR) = buf[i];
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} else {
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return(1);
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}
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}
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tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
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CHECK_NACK();
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if (!(tmp & I2C_STAT_SCD)) {
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REG(I2C_CON) = 0;
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return(1);
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}
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flush_rx();
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REG(I2C_STAT) = 0xffff;
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REG(I2C_CNT) = 0;
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REG(I2C_CON) = 0;
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return(0);
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}
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