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![Rob Herring](/assets/img/avatar_default.png)
Add support for AHCI controllers that are not PCI based. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Wolfgang Denk <wd@denx.de>
750 lines
18 KiB
C
750 lines
18 KiB
C
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006.
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* Author: Jason Jin<Jason.jin@freescale.com>
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* Zhang Wei<wei.zhang@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* with the reference on libata and ahci drvier in kernel
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <scsi.h>
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#include <ata.h>
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#include <linux/ctype.h>
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#include <ahci.h>
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struct ahci_probe_ent *probe_ent = NULL;
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hd_driveid_t *ataid[AHCI_MAX_PORTS];
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#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
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static inline u32 ahci_port_base(u32 base, u32 port)
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{
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return base + 0x100 + (port * 0x80);
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}
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static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
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unsigned int port_idx)
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{
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base = ahci_port_base(base, port_idx);
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port->cmd_addr = base;
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port->scr_addr = base + PORT_SCR;
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}
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#define msleep(a) udelay(a * 1000)
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#define ssleep(a) msleep(a * 1000)
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static int waiting_for_cmd_completed(volatile u8 *offset,
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int timeout_msec,
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u32 sign)
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{
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int i;
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u32 status;
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for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
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msleep(1);
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return (i < timeout_msec) ? 0 : -1;
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}
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static int ahci_host_init(struct ahci_probe_ent *probe_ent)
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{
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#ifndef CONFIG_SCSI_AHCI_PLAT
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pci_dev_t pdev = probe_ent->dev;
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u16 tmp16;
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unsigned short vendor;
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#endif
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volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
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u32 tmp, cap_save;
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int i, j;
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volatile u8 *port_mmio;
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cap_save = readl(mmio + HOST_CAP);
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cap_save &= ((1 << 28) | (1 << 17));
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cap_save |= (1 << 27);
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/* global controller reset */
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tmp = readl(mmio + HOST_CTL);
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if ((tmp & HOST_RESET) == 0)
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writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
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/* reset must complete within 1 second, or
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* the hardware should be considered fried.
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*/
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ssleep(1);
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tmp = readl(mmio + HOST_CTL);
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if (tmp & HOST_RESET) {
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debug("controller reset failed (0x%x)\n", tmp);
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return -1;
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}
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writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
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writel(cap_save, mmio + HOST_CAP);
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writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
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#ifndef CONFIG_SCSI_AHCI_PLAT
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pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
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if (vendor == PCI_VENDOR_ID_INTEL) {
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u16 tmp16;
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pci_read_config_word(pdev, 0x92, &tmp16);
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tmp16 |= 0xf;
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pci_write_config_word(pdev, 0x92, tmp16);
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}
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#endif
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probe_ent->cap = readl(mmio + HOST_CAP);
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probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
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probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
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debug("cap 0x%x port_map 0x%x n_ports %d\n",
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probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
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for (i = 0; i < probe_ent->n_ports; i++) {
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probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
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port_mmio = (u8 *) probe_ent->port[i].port_mmio;
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ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
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/* make sure port is not active */
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tmp = readl(port_mmio + PORT_CMD);
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if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
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PORT_CMD_FIS_RX | PORT_CMD_START)) {
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tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
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PORT_CMD_FIS_RX | PORT_CMD_START);
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writel_with_flush(tmp, port_mmio + PORT_CMD);
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/* spec says 500 msecs for each bit, so
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* this is slightly incorrect.
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*/
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msleep(500);
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}
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writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
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j = 0;
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while (j < 100) {
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msleep(10);
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tmp = readl(port_mmio + PORT_SCR_STAT);
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if ((tmp & 0xf) == 0x3)
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break;
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j++;
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}
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tmp = readl(port_mmio + PORT_SCR_ERR);
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debug("PORT_SCR_ERR 0x%x\n", tmp);
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writel(tmp, port_mmio + PORT_SCR_ERR);
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/* ack any pending irq events for this port */
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tmp = readl(port_mmio + PORT_IRQ_STAT);
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debug("PORT_IRQ_STAT 0x%x\n", tmp);
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if (tmp)
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writel(tmp, port_mmio + PORT_IRQ_STAT);
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writel(1 << i, mmio + HOST_IRQ_STAT);
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/* set irq mask (enables interrupts) */
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writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
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/*register linkup ports */
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tmp = readl(port_mmio + PORT_SCR_STAT);
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debug("Port %d status: 0x%x\n", i, tmp);
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if ((tmp & 0xf) == 0x03)
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probe_ent->link_port_map |= (0x01 << i);
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}
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tmp = readl(mmio + HOST_CTL);
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debug("HOST_CTL 0x%x\n", tmp);
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writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
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tmp = readl(mmio + HOST_CTL);
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debug("HOST_CTL 0x%x\n", tmp);
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#ifndef CONFIG_SCSI_AHCI_PLAT
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pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
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tmp |= PCI_COMMAND_MASTER;
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pci_write_config_word(pdev, PCI_COMMAND, tmp16);
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#endif
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return 0;
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}
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static void ahci_print_info(struct ahci_probe_ent *probe_ent)
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{
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#ifndef CONFIG_SCSI_AHCI_PLAT
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pci_dev_t pdev = probe_ent->dev;
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u16 cc;
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#endif
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volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
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u32 vers, cap, impl, speed;
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const char *speed_s;
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const char *scc_s;
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vers = readl(mmio + HOST_VERSION);
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cap = probe_ent->cap;
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impl = probe_ent->port_map;
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speed = (cap >> 20) & 0xf;
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if (speed == 1)
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speed_s = "1.5";
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else if (speed == 2)
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speed_s = "3";
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else
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speed_s = "?";
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#ifdef CONFIG_SCSI_AHCI_PLAT
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scc_s = "SATA";
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#else
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pci_read_config_word(pdev, 0x0a, &cc);
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if (cc == 0x0101)
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scc_s = "IDE";
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else if (cc == 0x0106)
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scc_s = "SATA";
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else if (cc == 0x0104)
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scc_s = "RAID";
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else
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scc_s = "unknown";
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#endif
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printf("AHCI %02x%02x.%02x%02x "
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"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
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(vers >> 24) & 0xff,
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(vers >> 16) & 0xff,
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(vers >> 8) & 0xff,
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vers & 0xff,
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((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
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printf("flags: "
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"%s%s%s%s%s%s"
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"%s%s%s%s%s%s%s\n",
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cap & (1 << 31) ? "64bit " : "",
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cap & (1 << 30) ? "ncq " : "",
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cap & (1 << 28) ? "ilck " : "",
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cap & (1 << 27) ? "stag " : "",
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cap & (1 << 26) ? "pm " : "",
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cap & (1 << 25) ? "led " : "",
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cap & (1 << 24) ? "clo " : "",
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cap & (1 << 19) ? "nz " : "",
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cap & (1 << 18) ? "only " : "",
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cap & (1 << 17) ? "pmp " : "",
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cap & (1 << 15) ? "pio " : "",
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cap & (1 << 14) ? "slum " : "",
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cap & (1 << 13) ? "part " : "");
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}
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#ifndef CONFIG_SCSI_AHCI_PLAT
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static int ahci_init_one(pci_dev_t pdev)
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{
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u16 vendor;
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int rc;
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memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
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probe_ent = malloc(sizeof(struct ahci_probe_ent));
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memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
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probe_ent->dev = pdev;
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probe_ent->host_flags = ATA_FLAG_SATA
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| ATA_FLAG_NO_LEGACY
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| ATA_FLAG_MMIO
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| ATA_FLAG_PIO_DMA
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| ATA_FLAG_NO_ATAPI;
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probe_ent->pio_mask = 0x1f;
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probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
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probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
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PCI_REGION_MEM);
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/* Take from kernel:
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* JMicron-specific fixup:
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* make sure we're in AHCI mode
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*/
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pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
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if (vendor == 0x197b)
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pci_write_config_byte(pdev, 0x41, 0xa1);
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/* initialize adapter */
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rc = ahci_host_init(probe_ent);
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if (rc)
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goto err_out;
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ahci_print_info(probe_ent);
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return 0;
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err_out:
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return rc;
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}
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#endif
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#define MAX_DATA_BYTE_COUNT (4*1024*1024)
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static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
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{
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struct ahci_ioports *pp = &(probe_ent->port[port]);
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struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
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u32 sg_count;
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int i;
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sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
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if (sg_count > AHCI_MAX_SG) {
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printf("Error:Too much sg!\n");
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return -1;
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}
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for (i = 0; i < sg_count; i++) {
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ahci_sg->addr =
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cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
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ahci_sg->addr_hi = 0;
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ahci_sg->flags_size = cpu_to_le32(0x3fffff &
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(buf_len < MAX_DATA_BYTE_COUNT
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? (buf_len - 1)
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: (MAX_DATA_BYTE_COUNT - 1)));
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ahci_sg++;
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buf_len -= MAX_DATA_BYTE_COUNT;
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}
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return sg_count;
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}
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static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
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{
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pp->cmd_slot->opts = cpu_to_le32(opts);
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pp->cmd_slot->status = 0;
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pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
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pp->cmd_slot->tbl_addr_hi = 0;
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}
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static void ahci_set_feature(u8 port)
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{
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struct ahci_ioports *pp = &(probe_ent->port[port]);
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volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
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u32 cmd_fis_len = 5; /* five dwords */
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u8 fis[20];
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/*set feature */
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memset(fis, 0, 20);
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fis[0] = 0x27;
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fis[1] = 1 << 7;
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fis[2] = ATA_CMD_SETF;
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fis[3] = SETFEATURES_XFER;
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fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
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memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
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ahci_fill_cmd_slot(pp, cmd_fis_len);
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writel(1, port_mmio + PORT_CMD_ISSUE);
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readl(port_mmio + PORT_CMD_ISSUE);
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if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
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printf("set feature error!\n");
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}
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}
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static int ahci_port_start(u8 port)
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{
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struct ahci_ioports *pp = &(probe_ent->port[port]);
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volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
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u32 port_status;
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u32 mem;
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debug("Enter start port: %d\n", port);
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port_status = readl(port_mmio + PORT_SCR_STAT);
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debug("Port %d status: %x\n", port, port_status);
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if ((port_status & 0xf) != 0x03) {
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printf("No Link on this port!\n");
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return -1;
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}
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mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
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if (!mem) {
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free(pp);
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printf("No mem for table!\n");
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return -ENOMEM;
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}
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mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
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memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
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/*
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* First item in chunk of DMA memory: 32-slot command table,
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* 32 bytes each in size
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*/
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pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
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debug("cmd_slot = 0x%x\n", pp->cmd_slot);
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mem += (AHCI_CMD_SLOT_SZ + 224);
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/*
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* Second item: Received-FIS area
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*/
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pp->rx_fis = mem;
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mem += AHCI_RX_FIS_SZ;
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/*
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* Third item: data area for storing a single command
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* and its scatter-gather table
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*/
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pp->cmd_tbl = mem;
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debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
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mem += AHCI_CMD_TBL_HDR;
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pp->cmd_tbl_sg = (struct ahci_sg *)mem;
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writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
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writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
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writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
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PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
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PORT_CMD_START, port_mmio + PORT_CMD);
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debug("Exit start port %d\n", port);
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return 0;
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}
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static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
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int buf_len)
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{
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struct ahci_ioports *pp = &(probe_ent->port[port]);
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volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
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u32 opts;
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u32 port_status;
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int sg_count;
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debug("Enter get_ahci_device_data: for port %d\n", port);
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if (port > probe_ent->n_ports) {
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printf("Invaild port number %d\n", port);
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return -1;
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}
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port_status = readl(port_mmio + PORT_SCR_STAT);
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if ((port_status & 0xf) != 0x03) {
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debug("No Link on port %d!\n", port);
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return -1;
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}
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memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
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sg_count = ahci_fill_sg(port, buf, buf_len);
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opts = (fis_len >> 2) | (sg_count << 16);
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ahci_fill_cmd_slot(pp, opts);
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writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
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if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
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printf("timeout exit!\n");
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return -1;
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}
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debug("get_ahci_device_data: %d byte transferred.\n",
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pp->cmd_slot->status);
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return 0;
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}
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static char *ata_id_strcpy(u16 *target, u16 *src, int len)
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{
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int i;
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for (i = 0; i < len / 2; i++)
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target[i] = swab16(src[i]);
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return (char *)target;
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}
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|
|
|
|
|
static void dump_ataid(hd_driveid_t *ataid)
|
|
{
|
|
debug("(49)ataid->capability = 0x%x\n", ataid->capability);
|
|
debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
|
|
debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
|
|
debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
|
|
debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
|
|
debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
|
|
debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
|
|
debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
|
|
debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
|
|
debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
|
|
debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
|
|
debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
|
|
debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
|
|
debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
|
|
debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
|
|
}
|
|
|
|
|
|
/*
|
|
* SCSI INQUIRY command operation.
|
|
*/
|
|
static int ata_scsiop_inquiry(ccb *pccb)
|
|
{
|
|
u8 hdr[] = {
|
|
0,
|
|
0,
|
|
0x5, /* claim SPC-3 version compatibility */
|
|
2,
|
|
95 - 4,
|
|
};
|
|
u8 fis[20];
|
|
u8 *tmpid;
|
|
u8 port;
|
|
|
|
/* Clean ccb data buffer */
|
|
memset(pccb->pdata, 0, pccb->datalen);
|
|
|
|
memcpy(pccb->pdata, hdr, sizeof(hdr));
|
|
|
|
if (pccb->datalen <= 35)
|
|
return 0;
|
|
|
|
memset(fis, 0, 20);
|
|
/* Construct the FIS */
|
|
fis[0] = 0x27; /* Host to device FIS. */
|
|
fis[1] = 1 << 7; /* Command FIS. */
|
|
fis[2] = ATA_CMD_IDENT; /* Command byte. */
|
|
|
|
/* Read id from sata */
|
|
port = pccb->target;
|
|
if (!(tmpid = malloc(sizeof(hd_driveid_t))))
|
|
return -ENOMEM;
|
|
|
|
if (get_ahci_device_data(port, (u8 *) & fis, 20,
|
|
tmpid, sizeof(hd_driveid_t))) {
|
|
debug("scsi_ahci: SCSI inquiry command failure.\n");
|
|
return -EIO;
|
|
}
|
|
|
|
if (ataid[port])
|
|
free(ataid[port]);
|
|
ataid[port] = (hd_driveid_t *) tmpid;
|
|
|
|
memcpy(&pccb->pdata[8], "ATA ", 8);
|
|
ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
|
|
ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
|
|
|
|
dump_ataid(ataid[port]);
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* SCSI READ10 command operation.
|
|
*/
|
|
static int ata_scsiop_read10(ccb * pccb)
|
|
{
|
|
u64 lba = 0;
|
|
u32 len = 0;
|
|
u8 fis[20];
|
|
|
|
lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
|
|
| (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
|
|
len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
|
|
|
|
/* For 10-byte and 16-byte SCSI R/W commands, transfer
|
|
* length 0 means transfer 0 block of data.
|
|
* However, for ATA R/W commands, sector count 0 means
|
|
* 256 or 65536 sectors, not 0 sectors as in SCSI.
|
|
*
|
|
* WARNING: one or two older ATA drives treat 0 as 0...
|
|
*/
|
|
if (!len)
|
|
return 0;
|
|
memset(fis, 0, 20);
|
|
|
|
/* Construct the FIS */
|
|
fis[0] = 0x27; /* Host to device FIS. */
|
|
fis[1] = 1 << 7; /* Command FIS. */
|
|
fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
|
|
|
|
/* LBA address, only support LBA28 in this driver */
|
|
fis[4] = pccb->cmd[5];
|
|
fis[5] = pccb->cmd[4];
|
|
fis[6] = pccb->cmd[3];
|
|
fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
|
|
|
|
/* Sector Count */
|
|
fis[12] = pccb->cmd[8];
|
|
fis[13] = pccb->cmd[7];
|
|
|
|
/* Read from ahci */
|
|
if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
|
|
pccb->pdata, pccb->datalen)) {
|
|
debug("scsi_ahci: SCSI READ10 command failure.\n");
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* SCSI READ CAPACITY10 command operation.
|
|
*/
|
|
static int ata_scsiop_read_capacity10(ccb *pccb)
|
|
{
|
|
u32 cap;
|
|
|
|
if (!ataid[pccb->target]) {
|
|
printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
|
|
"\tNo ATA info!\n"
|
|
"\tPlease run SCSI commmand INQUIRY firstly!\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
|
|
memcpy(pccb->pdata, &cap, sizeof(cap));
|
|
|
|
pccb->pdata[4] = pccb->pdata[5] = 0;
|
|
pccb->pdata[6] = 512 >> 8;
|
|
pccb->pdata[7] = 512 & 0xff;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* SCSI TEST UNIT READY command operation.
|
|
*/
|
|
static int ata_scsiop_test_unit_ready(ccb *pccb)
|
|
{
|
|
return (ataid[pccb->target]) ? 0 : -EPERM;
|
|
}
|
|
|
|
|
|
int scsi_exec(ccb *pccb)
|
|
{
|
|
int ret;
|
|
|
|
switch (pccb->cmd[0]) {
|
|
case SCSI_READ10:
|
|
ret = ata_scsiop_read10(pccb);
|
|
break;
|
|
case SCSI_RD_CAPAC:
|
|
ret = ata_scsiop_read_capacity10(pccb);
|
|
break;
|
|
case SCSI_TST_U_RDY:
|
|
ret = ata_scsiop_test_unit_ready(pccb);
|
|
break;
|
|
case SCSI_INQUIRY:
|
|
ret = ata_scsiop_inquiry(pccb);
|
|
break;
|
|
default:
|
|
printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
|
|
return FALSE;
|
|
}
|
|
|
|
if (ret) {
|
|
debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
|
|
return FALSE;
|
|
}
|
|
return TRUE;
|
|
|
|
}
|
|
|
|
|
|
void scsi_low_level_init(int busdevfunc)
|
|
{
|
|
int i;
|
|
u32 linkmap;
|
|
|
|
#ifndef CONFIG_SCSI_AHCI_PLAT
|
|
ahci_init_one(busdevfunc);
|
|
#endif
|
|
|
|
linkmap = probe_ent->link_port_map;
|
|
|
|
for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
|
|
if (((linkmap >> i) & 0x01)) {
|
|
if (ahci_port_start((u8) i)) {
|
|
printf("Can not start port %d\n", i);
|
|
continue;
|
|
}
|
|
ahci_set_feature((u8) i);
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SCSI_AHCI_PLAT
|
|
int ahci_init(u32 base)
|
|
{
|
|
int i, rc = 0;
|
|
u32 linkmap;
|
|
|
|
memset(ataid, 0, sizeof(ataid));
|
|
|
|
probe_ent = malloc(sizeof(struct ahci_probe_ent));
|
|
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
|
|
|
|
probe_ent->host_flags = ATA_FLAG_SATA
|
|
| ATA_FLAG_NO_LEGACY
|
|
| ATA_FLAG_MMIO
|
|
| ATA_FLAG_PIO_DMA
|
|
| ATA_FLAG_NO_ATAPI;
|
|
probe_ent->pio_mask = 0x1f;
|
|
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
|
|
|
|
probe_ent->mmio_base = base;
|
|
|
|
/* initialize adapter */
|
|
rc = ahci_host_init(probe_ent);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
ahci_print_info(probe_ent);
|
|
|
|
linkmap = probe_ent->link_port_map;
|
|
|
|
for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
|
|
if (((linkmap >> i) & 0x01)) {
|
|
if (ahci_port_start((u8) i)) {
|
|
printf("Can not start port %d\n", i);
|
|
continue;
|
|
}
|
|
ahci_set_feature((u8) i);
|
|
}
|
|
}
|
|
err_out:
|
|
return rc;
|
|
}
|
|
#endif
|
|
|
|
void scsi_bus_reset(void)
|
|
{
|
|
/*Not implement*/
|
|
}
|
|
|
|
|
|
void scsi_print_error(ccb * pccb)
|
|
{
|
|
/*The ahci error info can be read in the ahci driver*/
|
|
}
|