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https://github.com/brain-hackers/u-boot-brain
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26822fd23c
Convert the board to ethernet DM support. Adjust board file accordingly, as the board_eth_init() contains custom clock configuration required for this board to work. Furthermore, enable FEC1 clock to make FEC1 work as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
97 lines
2.4 KiB
C
97 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 samtec automotive software & electronics gmbh
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*
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* Configuration settings for the Samtec VIN|ING 2000 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "mx6_common.h"
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#ifdef CONFIG_SPL
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#include "imx6_spl.h"
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#endif
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(USB, usb, 0) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
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/* Physical Memory Map */
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* MMC Configuration */
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_SPEED 100000
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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/* Network */
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x0
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_PHY_ATHEROS
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#ifdef CONFIG_CMD_USB
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIE_IMX
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#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6)
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#endif
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#define CONFIG_IMX_THERMAL
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#define CONFIG_IMX6_PWM_PER_CLK 66000000
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#ifdef CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */
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/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
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#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#endif
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#endif /* __CONFIG_H */
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