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https://github.com/brain-hackers/u-boot-brain
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d93fbac512
For zynqmp qspi, frequencies up to 40MHz will work irrespective of feedback clock enabled or disabled. If we want higher than 40Mhz the feedback clock should be enabled. With spi-max-frequency 108MHz it is not working when the feedback clock is disabled. Change it to 40MHz so that it works irrespective of feedback clock enabled or disabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
80 lines
1.4 KiB
Plaintext
80 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP Mini Configuration
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*
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* (C) Copyright 2015 - 2020, Xilinx, Inc.
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*
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* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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/ {
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model = "ZynqMP MINI QSPI";
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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#size-cells = <1>;
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aliases {
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serial0 = &dcc;
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spi0 = &qspi;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@fffc0000 {
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device_type = "memory";
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reg = <0x0 0xfffc0000 0x40000>;
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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amba: amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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qspi: spi@ff0f0000 {
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compatible = "xlnx,zynqmp-qspi-1.0";
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status = "disabled";
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clock-names = "ref_clk", "pclk";
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clocks = <&misc_clk &misc_clk>;
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num-cs = <1>;
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reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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misc_clk: misc_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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};
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};
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&qspi {
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status = "okay";
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flash0: flash@0 {
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compatible = "n25q512a11", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <40000000>;
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};
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};
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&dcc {
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status = "okay";
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};
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