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https://github.com/brain-hackers/u-boot-brain
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bc0e8d7c5d
Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
22 lines
545 B
C
22 lines
545 B
C
/*
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* USB 3.0 DRD Controller
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define USB3_PHY_REF_SSP_EN BIT(29)
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#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16)
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/* KEYSTONE2 XHCI PHY register structure */
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struct keystone_xhci_phy {
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unsigned int phy_utmi; /* ctl0 */
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unsigned int phy_pipe; /* ctl1 */
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unsigned int phy_param_ctrl_1; /* ctl2 */
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unsigned int phy_param_ctrl_2; /* ctl3 */
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unsigned int phy_clock; /* ctl4 */
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unsigned int phy_pll; /* ctl5 */
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};
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