mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 08:43:45 +09:00
bc0e8d7c5d
Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
211 lines
6.5 KiB
C
211 lines
6.5 KiB
C
/*
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* Keystone2: Common SoC definitions, structures etc.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/sizes.h>
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#include <asm/io.h>
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#define REG(addr) (*(volatile unsigned int *)(addr))
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#define REG_P(addr) ((volatile unsigned int *)(addr))
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typedef volatile unsigned int dv_reg;
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typedef volatile unsigned int *dv_reg_p;
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#endif
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#define BIT(x) (1 << (x))
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#define KS2_DDRPHY_PIR_OFFSET 0x04
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#define KS2_DDRPHY_PGCR0_OFFSET 0x08
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#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
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#define KS2_DDRPHY_PGSR0_OFFSET 0x10
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#define KS2_DDRPHY_PGSR1_OFFSET 0x14
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#define KS2_DDRPHY_PLLCR_OFFSET 0x18
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#define KS2_DDRPHY_PTR0_OFFSET 0x1C
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#define KS2_DDRPHY_PTR1_OFFSET 0x20
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#define KS2_DDRPHY_PTR2_OFFSET 0x24
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#define KS2_DDRPHY_PTR3_OFFSET 0x28
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#define KS2_DDRPHY_PTR4_OFFSET 0x2C
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#define KS2_DDRPHY_DCR_OFFSET 0x44
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#define KS2_DDRPHY_DTPR0_OFFSET 0x48
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#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
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#define KS2_DDRPHY_DTPR2_OFFSET 0x50
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#define KS2_DDRPHY_MR0_OFFSET 0x54
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#define KS2_DDRPHY_MR1_OFFSET 0x58
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#define KS2_DDRPHY_MR2_OFFSET 0x5C
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#define KS2_DDRPHY_DTCR_OFFSET 0x68
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#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
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#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
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#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
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#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
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#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
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#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
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#define IODDRM_MASK 0x00000180
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#define ZCKSEL_MASK 0x01800000
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#define CL_MASK 0x00000072
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#define WR_MASK 0x00000E00
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#define BL_MASK 0x00000003
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#define RRMODE_MASK 0x00040000
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#define UDIMM_MASK 0x20000000
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#define BYTEMASK_MASK 0x0003FC00
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#define MPRDQ_MASK 0x00000080
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#define PDQ_MASK 0x00000070
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#define NOSRA_MASK 0x08000000
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#define ECC_MASK 0x00000001
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/* DDR3 definitions */
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#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
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#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
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#define KS2_DDR3A_DDRPHYC 0x02329000
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#define KS2_DDR3_MIDR_OFFSET 0x00
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#define KS2_DDR3_STATUS_OFFSET 0x04
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#define KS2_DDR3_SDCFG_OFFSET 0x08
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#define KS2_DDR3_SDRFC_OFFSET 0x10
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#define KS2_DDR3_SDTIM1_OFFSET 0x18
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#define KS2_DDR3_SDTIM2_OFFSET 0x1C
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#define KS2_DDR3_SDTIM3_OFFSET 0x20
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#define KS2_DDR3_SDTIM4_OFFSET 0x28
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#define KS2_DDR3_PMCTL_OFFSET 0x38
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#define KS2_DDR3_ZQCFG_OFFSET 0xC8
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#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
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#define KS2_UART0_BASE 0x02530c00
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#define KS2_UART1_BASE 0x02531000
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/* Boot Config */
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#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
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#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
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#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
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/* PSC */
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#define KS2_PSC_BASE 0x02350000
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#define KS2_LPSC_GEM_0 15
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#define KS2_LPSC_TETRIS 52
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#define KS2_TETRIS_PWR_DOMAIN 31
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/* Chip configuration unlock codes and registers */
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#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
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#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
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#define KS2_KICK0_MAGIC 0x83e70b13
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#define KS2_KICK1_MAGIC 0x95a4f1e0
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/* PLL control registers */
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#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
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#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
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#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
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#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
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#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
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#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
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#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
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#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
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#define KS2_PLL_CNTRL_BASE 0x02310000
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#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
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#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
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#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
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#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
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#define KS2_RSTCTRL_KEY 0x5a69
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#define KS2_RSTCTRL_MASK 0xffff0000
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#define KS2_RSTCTRL_SWRST 0xfffe0000
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#define KS2_RSTYPE_PLL_SOFT BIT(13)
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/* SPI */
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#define KS2_SPI0_BASE 0x21000400
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#define KS2_SPI1_BASE 0x21000600
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#define KS2_SPI2_BASE 0x21000800
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#define KS2_SPI_BASE KS2_SPI0_BASE
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/* AEMIF */
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#define KS2_AEMIF_CNTRL_BASE 0x21000a00
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
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/* Flag from ks2_debug options to check if DSPs need to stay ON */
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#define DBG_LEAVE_DSPS_ON 0x1
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/* Device speed */
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#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
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#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
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/* Queue manager */
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#define KS2_QM_BASE_ADDRESS 0x23a80000
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#define KS2_QM_CONF_BASE 0x02a02000
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#define KS2_QM_DESC_SETUP_BASE 0x02a03000
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#define KS2_QM_STATUS_RAM_BASE 0x02a06000
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#define KS2_QM_INTD_CONF_BASE 0x02a0c000
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#define KS2_QM_PDSP1_CMD_BASE 0x02a20000
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#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
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#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
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#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
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#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
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#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
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#define KS2_QM_LINK_RAM_BASE 0x00100000
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#define KS2_QM_REGION_NUM 64
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#define KS2_QM_QPOOL_NUM 4000
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/* MSMC control */
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#define KS2_MSMC_CTRL_BASE 0x0bc00000
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/* USB */
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#define KS2_USB_SS_BASE 0x02680000
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#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
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#define KS2_DEV_USB_PHY_BASE 0x02620738
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#define KS2_USB_PHY_CFG_BASE 0x02630000
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/hardware-k2hk.h>
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#endif
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#ifdef CONFIG_SOC_K2E
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#include <asm/arch/hardware-k2e.h>
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#endif
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#ifndef __ASSEMBLY__
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static inline int cpu_is_k2hk(void)
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{
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unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
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unsigned int part_no = (jtag_id >> 12) & 0xffff;
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return (part_no == 0xb981) ? 1 : 0;
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}
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static inline int cpu_is_k2e(void)
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{
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unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
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unsigned int part_no = (jtag_id >> 12) & 0xffff;
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return (part_no == 0xb9a6) ? 1 : 0;
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}
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static inline int cpu_revision(void)
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{
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unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
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unsigned int rev = (jtag_id >> 28) & 0xf;
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return rev;
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}
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int cpu_to_bus(u32 *ptr, u32 length);
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void sdelay(unsigned long);
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#endif
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#endif /* __ASM_ARCH_HARDWARE_H */
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