Mingkai Hu bbc8e053ba armv8/ls1043a: Implement workaround for erratum A009660 ... Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-02-24 08:40:56 -08:00
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asm	armv8/ls1043a: Implement workaround for erratum A009660	2016-02-24 08:40:56 -08:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00