mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 04:49:42 +09:00
14d5aeff77
This adds initial minimal support for the Toradex Verdin iMX8M Mini Quad 2GB WB IT V1.0A module. They are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports booting from the on-module eMMC only, SDP support is disabled for now due to missing i.MX 8M Mini USB support. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Ethernet - GPIOs - I2C Boot sequence is: SPL ---> ATF (TF-A) ---> U-boot proper ATF, U-boot proper and u-boot.dtb images are packed into a FIT image, loaded by SPL. Boot: U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) Normal Boot Trying to boot from MMC1 NOTICE: Configuring TZASC380 NOTICE: RDC off NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty NOTICE: BL31: Built : 01:11:41, Jan 25 2020 NOTICE: sip svc init U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz Reset cause: POR DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial# 06535149 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Verdin iMX8MM # Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
74 lines
1.4 KiB
C
74 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 Toradex
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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#if IS_ENABLED(CONFIG_FEC_MXC)
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC))
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setup_fec();
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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return 0;
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}
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#endif
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