mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
bb0dc1084f
The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
131 lines
3.3 KiB
C
131 lines
3.3 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <mmc.h>
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#include <malloc.h>
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/*
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* The environment variables are written to just after the u-boot image
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* on SDCard, so we must read the MBR to get the start address and code
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* length of the u-boot image, then calculate the address of the env.
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*/
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#define ESDHC_BOOT_IMAGE_SIZE 0x48
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#define ESDHC_BOOT_IMAGE_ADDR 0x50
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#define MBRDBR_BOOT_SIG_55 0x1fe
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#define MBRDBR_BOOT_SIG_AA 0x1ff
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#define CONFIG_CFG_DATA_SECTOR 0
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/*
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* The main entry for mmc booting. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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* from mmc into SDRAM and starts it from there.
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*/
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void __noreturn mmc_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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uint blk_start, blk_cnt, err;
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u32 blklen;
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uchar *tmp_buf;
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uchar val;
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uint i, byte_num;
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u32 offset, code_len;
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struct mmc *mmc;
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mmc = find_mmc_device(0);
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if (!mmc) {
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puts("spl: mmc device not found!!\n");
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hang();
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}
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blklen = mmc->read_bl_len;
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tmp_buf = malloc(blklen);
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if (!tmp_buf) {
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puts("spl: malloc memory failed!!\n");
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hang();
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}
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memset(tmp_buf, 0, blklen);
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/*
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* Read source addr from sd card
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*/
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err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
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if (err != 1) {
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puts("spl: mmc read failed!!\n");
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free(tmp_buf);
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hang();
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}
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val = *(tmp_buf + MBRDBR_BOOT_SIG_55);
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if (0x55 != val) {
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puts("spl: mmc signature is not valid!!\n");
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free(tmp_buf);
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hang();
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}
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val = *(tmp_buf + MBRDBR_BOOT_SIG_AA);
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if (0xAA != val) {
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puts("spl: mmc signature is not valid!!\n");
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free(tmp_buf);
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hang();
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}
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byte_num = 4;
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offset = 0;
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for (i = 0; i < byte_num; i++) {
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val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i);
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offset = (offset << 8) + val;
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}
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offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
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/* Get the code size from offset 0x48 */
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byte_num = 4;
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code_len = 0;
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for (i = 0; i < byte_num; i++) {
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val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i);
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code_len = (code_len << 8) + val;
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}
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code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS;
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/*
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* Load U-Boot image from mmc into RAM
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*/
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blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
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blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
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err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
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(uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
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if (err != blk_cnt) {
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puts("spl: mmc read failed!!\n");
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free(tmp_buf);
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hang();
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}
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/*
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* Clean d-cache and invalidate i-cache, to
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* make sure that no stale data is executed.
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*/
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flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE);
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/*
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* Jump to U-Boot image
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*/
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uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START;
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(*uboot)();
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}
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