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https://github.com/brain-hackers/u-boot-brain
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bb0dc1084f
The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
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| .. | ||
| 74xx_7xx | ||
| mpc5xx | ||
| mpc5xxx | ||
| mpc8xx | ||
| mpc8xxx | ||
| mpc83xx | ||
| mpc85xx | ||
| mpc86xx | ||
| mpc512x | ||
| mpc824x | ||
| mpc8260 | ||
| ppc4xx | ||