mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-06 11:30:47 +09:00
06d336cca2
There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot file of the same name
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ACH_ASM_SANDYBRIDGE_H
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#define _ACH_ASM_SANDYBRIDGE_H
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/* Chipset types */
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#define SANDYBRIDGE_MOBILE 0
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#define SANDYBRIDGE_DESKTOP 1
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#define SANDYBRIDGE_SERVER 2
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/* Device ID for SandyBridge and IvyBridge */
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#define BASE_REV_SNB 0x00
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#define BASE_REV_IVB 0x50
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#define BASE_REV_MASK 0x50
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/* SandyBridge CPU stepping */
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#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
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#define SNB_STEP_D1 (BASE_REV_SNB + 6)
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#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
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/* IvyBridge CPU stepping */
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#define IVB_STEP_A0 (BASE_REV_IVB + 0)
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#define IVB_STEP_B0 (BASE_REV_IVB + 2)
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#define IVB_STEP_C0 (BASE_REV_IVB + 4)
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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/* Intel Enhanced Debug region must be 4MB */
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#define IED_SIZE 0x400000
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/* Northbridge BARs */
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#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
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#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
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#define DEFAULT_RCBABASE 0xfed1c000
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/* 4 KB per PCIe device */
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#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define X60BAR 0x60
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#define GGC 0x50 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_PEG60 (1 << 13)
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#define DEVEN_IGD (1 << 4)
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#define DEVEN_PEG10 (1 << 3)
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#define DEVEN_PEG11 (1 << 2)
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#define DEVEN_PEG12 (1 << 1)
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#define DEVEN_HOST (1 << 0)
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#define PAM0 0x80
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#define PAM1 0x81
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#define PAM2 0x82
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#define PAM3 0x83
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#define PAM4 0x84
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#define PAM5 0x85
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#define PAM6 0x86
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#define LAC 0x87 /* Legacy Access Control */
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#define SMRAM 0x88 /* System Management RAM Control */
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define TOM 0xa0
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#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
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#define TSEG 0xb8 /* TSEG base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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#define SKPAD 0xdc /* Scratchpad Data */
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/* Device 0:1.0 PCI configuration space (PCI Express) */
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#define BCTRL1 0x3e /* 16bit */
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define MSAC 0x62 /* Multi Size Aperture Control */
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#define SWSCI 0xe8 /* SWSCI enable */
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#define ASLS 0xfc /* OpRegion Base */
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/*
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* MCHBAR
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*/
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#define SSKPD 0x5d14 /* 16bit (scratchpad) */
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#define BIOS_RESET_CPL 0x5da8 /* 8bit */
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/*
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* DMIBAR
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*/
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#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
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/**
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* bridge_silicon_revision() - Get the Northbridge revision
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*
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* @dev: Northbridge device
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* @return revision ID (bits 3:0) and bridge ID (bits 7:4)
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*/
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int bridge_silicon_revision(struct udevice *dev);
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void report_platform_info(struct udevice *dev);
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void sandybridge_early_init(int chipset_type);
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#endif
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