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https://github.com/brain-hackers/u-boot-brain
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![Ang, Chee Hong](/assets/img/avatar_default.png)
Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
128 lines
3.5 KiB
C
128 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*/
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#include <fpga.h>
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#ifndef _ALTERA_H_
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#define _ALTERA_H_
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/*
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* For the StratixV FPGA programming via SPI, the following
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* information is coded in the 32bit cookie:
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* Bit 31 ... Bit 0
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* SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
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*/
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#define FPGA_COOKIE(bus, dev, config, done) \
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(((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
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#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff)
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#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff)
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#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff)
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#define COOKIE2DONE(c) ((c) & 0xff)
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enum altera_iface {
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/* insert all new types after this */
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min_altera_iface_type,
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/* serial data and external clock */
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passive_serial,
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/* parallel data */
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passive_parallel_synchronous,
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/* parallel data */
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passive_parallel_asynchronous,
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/* serial data w/ internal clock (not used) */
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passive_serial_asynchronous,
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/* jtag/tap serial (not used ) */
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altera_jtag_mode,
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/* fast passive parallel (FPP) */
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fast_passive_parallel,
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/* fast passive parallel with security (FPPS) */
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fast_passive_parallel_security,
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/* secure device manager (SDM) mailbox */
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secure_device_manager_mailbox,
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/* insert all new types before this */
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max_altera_iface_type,
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};
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enum altera_family {
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/* insert all new types after this */
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min_altera_type,
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/* ACEX1K Family */
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Altera_ACEX1K,
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/* CYCLONII Family */
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Altera_CYC2,
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/* StratixII Family */
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Altera_StratixII,
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/* StratixV Family */
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Altera_StratixV,
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/* Stratix10 Family */
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Intel_FPGA_Stratix10,
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/* SoCFPGA Family */
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Altera_SoCFPGA,
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/* Add new models here */
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/* insert all new types before this */
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max_altera_type,
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};
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typedef struct {
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/* part type */
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enum altera_family family;
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/* interface type */
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enum altera_iface iface;
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/* bytes of data part can accept */
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size_t size;
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/* interface function table */
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void *iface_fns;
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/* base interface address */
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void *base;
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/* implementation specific cookie */
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int cookie;
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} Altera_desc;
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/* Generic Altera Functions
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*********************************************************************/
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extern int altera_load(Altera_desc *desc, const void *image, size_t size);
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extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
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extern int altera_info(Altera_desc *desc);
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/* Board specific implementation specific function types
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*********************************************************************/
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typedef int (*Altera_pre_fn)( int cookie );
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typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
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typedef int (*Altera_status_fn)( int cookie );
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typedef int (*Altera_done_fn)( int cookie );
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typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
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typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
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typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
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typedef int (*Altera_abort_fn)( int cookie );
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typedef int (*Altera_post_fn)( int cookie );
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typedef struct {
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Altera_pre_fn pre;
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Altera_config_fn config;
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Altera_status_fn status;
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Altera_done_fn done;
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Altera_clk_fn clk;
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Altera_data_fn data;
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Altera_write_fn write;
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Altera_abort_fn abort;
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Altera_post_fn post;
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} altera_board_specific_func;
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#ifdef CONFIG_FPGA_SOCFPGA
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int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
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#endif
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#ifdef CONFIG_FPGA_STRATIX_V
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int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
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#endif
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#ifdef CONFIG_FPGA_STRATIX10
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int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
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#endif
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#endif /* _ALTERA_H_ */
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