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https://github.com/brain-hackers/u-boot-brain
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6385b28116
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
463 lines
9.5 KiB
C
463 lines
9.5 KiB
C
/*
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* (C) Copyright 2007
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* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <spartan2.h>
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#include <spartan3.h>
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#include <command.h>
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#include "fpga.h"
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#include "pmc440.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA)
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#define USE_SP_CODE
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#ifdef USE_SP_CODE
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Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_init_fn,
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NULL, /* err */
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fpga_done_fn,
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fpga_clk_fn,
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fpga_cs_fn,
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fpga_wr_fn,
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NULL, /* rdata */
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fpga_wdata_fn,
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fpga_busy_fn,
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fpga_abort_fn,
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fpga_post_config_fn,
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};
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#else
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Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_clk_fn,
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fpga_init_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_post_config_fn,
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};
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#endif
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Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
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ngcc_fpga_pre_config_fn,
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ngcc_fpga_pgm_fn,
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ngcc_fpga_clk_fn,
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ngcc_fpga_init_fn,
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ngcc_fpga_done_fn,
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ngcc_fpga_wr_fn,
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ngcc_fpga_post_config_fn
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};
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Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
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XILINX_XC3S1200E_DESC(
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#ifdef USE_SP_CODE
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slave_parallel,
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#else
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slave_serial,
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#endif
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(void *)&pmc440_fpga_fns,
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0),
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XILINX_XC2S200_DESC(
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slave_serial,
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(void *)&ngcc_fpga_fns,
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0)
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};
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/*
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* Set the active-low FPGA reset signal.
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*/
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void fpga_reset(int assert)
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{
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debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
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if (assert) {
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
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debug("asserted\n");
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} else {
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
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debug("deasserted\n");
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}
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}
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/*
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* Initialize the SelectMap interface. We assume that the mode and the
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* initial state of all of the port pins have already been set!
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*/
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void fpga_serialslave_init(void)
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{
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debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
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__LINE__);
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fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
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}
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/*
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* Set the FPGA's active-low SelectMap program line to the specified level
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*/
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int fpga_pgm_fn(int assert, int flush, int cookie)
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{
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debug("%s:%d: FPGA PROGRAM ",
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__FUNCTION__, __LINE__);
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if (assert) {
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
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debug("asserted\n");
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} else {
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
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debug("deasserted\n");
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}
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return assert;
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}
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/*
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* Test the state of the active-low FPGA INIT line. Return 1 on INIT
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* asserted (low).
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*/
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int fpga_init_fn(int cookie)
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{
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if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
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return 0;
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else
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return 1;
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}
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#ifdef USE_SP_CODE
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int fpga_abort_fn(int cookie)
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{
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return 0;
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}
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int fpga_cs_fn(int assert_cs, int flush, int cookie)
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{
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return assert_cs;
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}
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int fpga_busy_fn(int cookie)
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{
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return 1;
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}
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#endif
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/*
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* Test the state of the active-high FPGA DONE pin
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*/
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int fpga_done_fn(int cookie)
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{
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if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
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return 1;
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else
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return 0;
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}
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/*
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* FPGA pre-configuration function. Just make sure that
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* FPGA reset is asserted to keep the FPGA from starting up after
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* configuration.
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*/
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int fpga_pre_config_fn(int cookie)
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{
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debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
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fpga_reset(TRUE);
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/* release init# */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
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/* disable PLD IOs */
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
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return 0;
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}
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/*
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* FPGA post configuration function. Blip the FPGA reset line and then see if
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* the FPGA appears to be running.
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*/
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int fpga_post_config_fn(int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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int rc=0;
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char *s;
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debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
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/* enable PLD0..7 pins */
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
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fpga_reset(TRUE);
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udelay (100);
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fpga_reset(FALSE);
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udelay (100);
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FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
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/* NGCC/CANDES only: enable ledlink */
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if ((s = getenv("bd_type")) &&
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((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
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FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
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return rc;
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}
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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if (assert_clk)
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
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else
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
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return assert_clk;
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}
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int fpga_wr_fn(int assert_write, int flush, int cookie)
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{
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if (assert_write)
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
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else
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
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return assert_write;
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}
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#ifdef USE_SP_CODE
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int fpga_wdata_fn(uchar data, int flush, int cookie)
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{
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uchar val = data;
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ulong or = in_be32((void*)GPIO1_OR);
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int i = 7;
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do {
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/* Write data */
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if (val & 0x80)
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or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
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else
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or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
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out_be32((void*)GPIO1_OR, or);
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/* Assert the clock */
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or |= GPIO1_FPGA_CLK;
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out_be32((void*)GPIO1_OR, or);
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val <<= 1;
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i --;
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} while (i > 0);
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/* Write last data bit (the 8th clock comes from the sp_load() code */
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if (val & 0x80)
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or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
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else
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or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
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out_be32((void*)GPIO1_OR, or);
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return 0;
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}
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#endif
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#define NGCC_FPGA_PRG CLOCK_EN
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#define NGCC_FPGA_DATA RESET_OUT
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#define NGCC_FPGA_DONE CLOCK_IN
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#define NGCC_FPGA_INIT IRIGB_R_IN
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#define NGCC_FPGA_CLK CLOCK_OUT
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void ngcc_fpga_serialslave_init(void)
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{
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debug("%s:%d: Initialize serial slave interface\n",
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__FUNCTION__, __LINE__);
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/* make sure program pin is inactive */
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ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
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}
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/*
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* Set the active-low FPGA reset signal.
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*/
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void ngcc_fpga_reset(int assert)
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{
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debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
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if (assert) {
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FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
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debug("asserted\n");
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} else {
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FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
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debug("deasserted\n");
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}
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}
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/*
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* Set the FPGA's active-low SelectMap program line to the specified level
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*/
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int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
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if (assert) {
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FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
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debug("asserted\n");
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} else {
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FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
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debug("deasserted\n");
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}
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return assert;
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}
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/*
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* Test the state of the active-low FPGA INIT line. Return 1 on INIT
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* asserted (low).
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*/
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int ngcc_fpga_init_fn(int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
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if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
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debug("high\n");
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return 0;
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} else {
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debug("low\n");
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return 1;
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}
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}
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/*
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* Test the state of the active-high FPGA DONE pin
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*/
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int ngcc_fpga_done_fn(int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
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if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
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debug("DONE high\n");
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return 1;
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} else {
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debug("low\n");
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return 0;
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}
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}
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/*
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* FPGA pre-configuration function.
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*/
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int ngcc_fpga_pre_config_fn(int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
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ngcc_fpga_reset(TRUE);
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FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
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ngcc_fpga_reset(TRUE);
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return 0;
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}
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/*
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* FPGA post configuration function. Blip the FPGA reset line and then see if
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* the FPGA appears to be running.
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*/
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int ngcc_fpga_post_config_fn(int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
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udelay (100);
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ngcc_fpga_reset(FALSE);
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FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
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return 0;
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}
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int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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if (assert_clk)
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FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
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else
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FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
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return assert_clk;
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}
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int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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if (assert_write)
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FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
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else
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FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
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return assert_write;
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}
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/*
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* Initialize the fpga. Return 1 on success, 0 on failure.
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*/
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int pmc440_init_fpga(void)
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{
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char *s;
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debug("%s:%d: Initialize FPGA interface\n",
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__FUNCTION__, __LINE__);
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fpga_init();
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fpga_serialslave_init ();
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debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
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fpga_add (fpga_xilinx, &fpga[0]);
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/* NGCC only */
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if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
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ngcc_fpga_serialslave_init ();
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debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
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fpga_add (fpga_xilinx, &fpga[1]);
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}
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return 0;
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}
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#endif /* CONFIG_FPGA */
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