mirror of
https://github.com/brain-hackers/u-boot-brain
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f3ee25859e
These files were autogenerated by EPSON configuration tools. This patch replaces the autogenerated file headers by the GPL license notice. This change is done with the explicit permission of Epson Research & Development / IC Software Development. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
61 lines
3.2 KiB
C
61 lines
3.2 KiB
C
/*
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* Copyright (c) 2000,2001 Epson Research and Development, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Generic Header information generated by 13704CFG.EXE (Build 10)
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* Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
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*/
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static S1D_REGS regs_13704_320_240_4bpp[] =
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{
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{ 0x00, 0x00 }, /* Revision Code Register */
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{ 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */
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{ 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */
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{ 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */
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{ 0x04, 0x27 }, /* Horizontal Panel Size Register */
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{ 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
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{ 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
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{ 0x07, 0x00 }, /* FPLINE Start Position Register */
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{ 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
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{ 0x09, 0x00 }, /* FPFRAME Start Position Register */
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{ 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
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{ 0x0B, 0x00 }, /* MOD Rate Register */
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{ 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
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{ 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
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{ 0x0E, 0x00 }, /* Not Used */
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{ 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
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{ 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
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{ 0x11, 0x00 }, /* Not Used */
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{ 0x12, 0x00 }, /* Memory Address Offset Register */
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{ 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
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{ 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
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{ 0x15, 0x00 }, /* Look-Up Table Address Register */
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{ 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
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{ 0x17, 0x00 }, /* Look-Up Table Data Register */
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{ 0x18, 0x01 }, /* GPIO Configuration Control Register */
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{ 0x19, 0x01 }, /* GPIO Status/Control Register */
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{ 0x1A, 0x00 }, /* Scratch Pad Register */
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{ 0x1B, 0x00 }, /* SwivelView Mode Register */
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{ 0x1C, 0xA0 }, /* Line Byte Count Register */
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{ 0x1D, 0x00 }, /* Not Used */
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{ 0x1E, 0x00 }, /* Not Used */
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{ 0x1F, 0x00 }, /* Not Used */
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};
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