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https://github.com/brain-hackers/u-boot-brain
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859a86a25c
With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/* LAW(Local Access Window) configuration:
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* 0000_0000-0800_0000: DDR(128M) -or- larger
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* f000_0000-f3ff_ffff: PCI(256M)
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* f400_0000-f7ff_ffff: RapidIO(128M)
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* f800_0000-ffff_ffff: localbus(128M)
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* f800_0000-fbff_ffff: LBC SDRAM(64M)
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* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
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* fdf0_0000-fdff_ffff: CCSRBAR(1M)
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* fe00_0000-ffff_ffff: Flash(32M)
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* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
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* Window.
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* Note: If flash is 8M at default position(last 8M),no LAW needed.
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*/
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struct law_entry law_table[] = {
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#ifndef CONFIG_SPD_EEPROM
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SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
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#endif
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SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
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#ifndef CONFIG_RAM_AS_FLASH
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SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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