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https://github.com/brain-hackers/u-boot-brain
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![Marc Ferland](/assets/img/avatar_default.png)
This patch converts the dart6ul ethernet support to DM_ETH and cleans up the legacy ethernet code. The clean up, more specifically: * moves the fec2 node and pin definition to the carrier board DTS since the phy associated with it is on the carrier board and not on the SoM; * add the reset pin associated to each phy; * separate the ethernet, mdio and reset pins of each fec so that they are easier to reference; * add clock properties to the phy nodes since they are connected to the 50Mhz ENET[12]_TX_CLK clock of the SoC; * remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
214 lines
5.5 KiB
C
214 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2019 Variscite Ltd.
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/crm_regs.h>
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#include <fsl_esdhc_imx.h>
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x000c0000,
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};
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_odt0 = 0x00000030,
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.dram_odt1 = 0x00000030,
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.dram_sdba2 = 0x00000000,
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.dram_sdclk_0 = 0x00000008,
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.dram_sdqs0 = 0x00000038,
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.dram_sdqs1 = 0x00000030,
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.dram_reset = 0x00000030,
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};
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpdgctrl0 = 0x414C0158,
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.p0_mprddlctl = 0x40403A3A,
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.p0_mpwrdlctl = 0x40405A56,
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};
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struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs_density = 20,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 800,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xFFFFFFFF, &ccm->CCGR0);
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writel(0xFFFFFFFF, &ccm->CCGR1);
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writel(0xFFFFFFFF, &ccm->CCGR2);
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writel(0xFFFFFFFF, &ccm->CCGR3);
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writel(0xFFFFFFFF, &ccm->CCGR4);
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writel(0xFFFFFFFF, &ccm->CCGR5);
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writel(0xFFFFFFFF, &ccm->CCGR6);
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writel(0xFFFFFFFF, &ccm->CCGR7);
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/* Enable Audio Clock for SOM codec */
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writel(0x01130100, (long *)CCM_CCOSR);
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}
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static void spl_dram_init(void)
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{
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#ifndef CONFIG_NAND_MXS
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#endif
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static struct fsl_esdhc_cfg usdhc_cfg[] = {
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{
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.esdhc_base = USDHC1_BASE_ADDR,
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.max_bus_width = 4,
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},
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#ifndef CONFIG_NAND_MXS
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{
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.esdhc_base = USDHC2_BASE_ADDR,
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.max_bus_width = 8,
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},
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#endif
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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int board_mmc_init(struct bd_info *bis)
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{
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int i, ret;
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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SETUP_IOMUX_PADS(usdhc1_pads);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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#ifndef CONFIG_NAND_MXS
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case 1:
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SETUP_IOMUX_PADS(usdhc2_pads);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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break;
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#endif
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default:
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printf("Warning - USDHC%d controller not supporting\n",
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i + 1);
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return 0;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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/* setup GP timer */
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timer_init();
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setup_iomux_uart();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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