mirror of
https://github.com/brain-hackers/u-boot-brain
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ba6a169811
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* (C) Copyright 2013
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* Andre Przywara, Linaro
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*
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* Routines to transition ARMv7 processors from secure into non-secure state
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* needed to enable ARMv7 virtualization for current hypervisors
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/gic.h>
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#include <asm/io.h>
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unsigned long gic_dist_addr;
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static unsigned int read_id_pfr1(void)
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{
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unsigned int reg;
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asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
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return reg;
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}
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static unsigned long get_gicd_base_address(void)
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{
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#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
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return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
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#else
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unsigned midr;
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unsigned periphbase;
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/* check whether we are an Cortex-A15 or A7.
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* The actual HYP switch should work with all CPUs supporting
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* the virtualization extension, but we need the GIC address,
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* which we know only for sure for those two CPUs.
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*/
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asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
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switch (midr & MIDR_PRIMARY_PART_MASK) {
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case MIDR_CORTEX_A9_R0P1:
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case MIDR_CORTEX_A15_R0P0:
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case MIDR_CORTEX_A7_R0P0:
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break;
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default:
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printf("nonsec: could not determine GIC address.\n");
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return -1;
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}
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/* get the GIC base address from the CBAR register */
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asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
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/* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
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* encode this). Bail out here since we cannot access this without
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* enabling paging.
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*/
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if ((periphbase & 0xff) != 0) {
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printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");
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return -1;
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}
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return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
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#endif
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}
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static void kick_secondary_cpus_gic(unsigned long gicdaddr)
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{
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/* kick all CPUs (except this one) by writing to GICD_SGIR */
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writel(1U << 24, gicdaddr + GICD_SGIR);
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}
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void __weak smp_kick_all_cpus(void)
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{
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kick_secondary_cpus_gic(gic_dist_addr);
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}
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int armv7_switch_nonsec(void)
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{
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unsigned int reg;
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unsigned itlinesnr, i;
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/* check whether the CPU supports the security extensions */
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reg = read_id_pfr1();
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if ((reg & 0xF0) == 0) {
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printf("nonsec: Security extensions not implemented.\n");
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return -1;
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}
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/* the SCR register will be set directly in the monitor mode handler,
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* according to the spec one should not tinker with it in secure state
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* in SVC mode. Do not try to read it once in non-secure state,
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* any access to it will trap.
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*/
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gic_dist_addr = get_gicd_base_address();
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if (gic_dist_addr == -1)
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return -1;
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/* enable the GIC distributor */
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writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
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gic_dist_addr + GICD_CTLR);
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/* TYPER[4:0] contains an encoded number of available interrupts */
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itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
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/* set all bits in the GIC group registers to one to allow access
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* from non-secure state. The first 32 interrupts are private per
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* CPU and will be set later when enabling the GIC for each core
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*/
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for (i = 1; i <= itlinesnr; i++)
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writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
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smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
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smp_kick_all_cpus();
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/* call the non-sec switching code on this CPU also */
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_nonsec_init();
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return 0;
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}
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