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https://github.com/brain-hackers/u-boot-brain
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62d7fe7c91
This patch adds AM33xx emif/ddr support along with board specific defines. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
148 lines
4.0 KiB
C
148 lines
4.0 KiB
C
/*
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* DDR Configuration for AM33xx devices.
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*
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* Copyright (C) 2011 Texas Instruments Incorporated -
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http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed .as is. WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/io.h>
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/**
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* Base address for EMIF instances
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*/
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static struct emif_regs *emif_reg = {
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(struct emif_regs *)EMIF4_0_CFG_BASE};
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/**
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* Base address for DDR instance
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*/
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static struct ddr_regs *ddr_reg[2] = {
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(struct ddr_regs *)DDR_PHY_BASE_ADDR,
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(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
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/**
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* Base address for ddr io control instances
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*/
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static struct ddr_cmdtctrl *ioctrl_reg = {
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(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
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/**
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* As a convention, all functions here return 0 on success
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* -1 on failure.
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*/
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/**
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* Configure SDRAM
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*/
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int config_sdram(struct sdram_config *cfg)
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{
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writel(cfg->sdrcr, &emif_reg->sdrcr);
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writel(cfg->sdrcr2, &emif_reg->sdrcr2);
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writel(cfg->refresh, &emif_reg->sdrrcr);
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writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
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return 0;
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}
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/**
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* Set SDRAM timings
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*/
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int set_sdram_timings(struct sdram_timing *t)
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{
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writel(t->time1, &emif_reg->sdrtim1);
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writel(t->time1_sh, &emif_reg->sdrtim1sr);
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writel(t->time2, &emif_reg->sdrtim2);
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writel(t->time2_sh, &emif_reg->sdrtim2sr);
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writel(t->time3, &emif_reg->sdrtim3);
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writel(t->time3_sh, &emif_reg->sdrtim3sr);
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return 0;
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}
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/**
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* Configure DDR PHY
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*/
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int config_ddr_phy(struct ddr_phy_control *p)
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{
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writel(p->reg, &emif_reg->ddrphycr);
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writel(p->reg_sh, &emif_reg->ddrphycsr);
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return 0;
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}
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/**
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* Configure DDR CMD control registers
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*/
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int config_cmd_ctrl(struct cmd_control *cmd)
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{
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writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
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writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
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writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
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writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
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writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
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writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
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writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
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writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
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writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
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writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
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writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
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writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
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writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
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writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
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writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
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return 0;
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}
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/**
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* Configure DDR DATA registers
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*/
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int config_ddr_data(int macrono, struct ddr_data *data)
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{
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writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
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writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
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writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
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writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
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writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
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writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
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writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
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writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
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writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
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writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
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writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
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writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
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writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
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return 0;
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}
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int config_io_ctrl(struct ddr_ioctrl *ioctrl)
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{
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writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
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writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
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writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
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writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
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writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
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return 0;
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}
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