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https://github.com/brain-hackers/u-boot-brain
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![Shengzhou Liu](/assets/img/avatar_default.png)
T2081 QDS is a high-performance computing evaluation, development and test platform supporting the T2081 QorIQ Power Architecture processor. T2081QDS board Overview ----------------------- - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC) - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving - Ethernet interfaces: - Two on-board 10M/100M/1G bps RGMII ports - Two 10Gbps XFI with on-board SFP+ cage - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card - Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC - SerDes: - 8 lanes up to 10.3125GHz - Supports SGMII, HiGig, XFI, XAUI and Aurora debug, - IFC: - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) - USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - PCIe: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - eSDHC: - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and voltage translators - I2C: - Four I2C controllers. - UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
42 lines
906 B
INI
42 lines
906 B
INI
#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Refer doc/README.pblimage for more details about how-to configure
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# and create PBL boot image
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#
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#PBI commands
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#Initialize CPC1
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09010000 00200400
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09138000 00000000
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091380c0 00000100
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#512KB SRAM
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09010100 00000000
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09010104 fff80009
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09010f00 08000000
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#enable CPC1
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09010000 80000000
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#Configure LAW for CPC1
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09000d00 00000000
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09000d04 fff80000
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09000d08 81000012
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#Initialize eSPI controller, default configuration is slow for eSPI to
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#load data, this configuration comes from u-boot eSPI driver.
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09110000 80000403
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09110020 2d170008
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09110024 00100008
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09110028 00100008
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0911002c 00100008
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#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
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094fc030 00008148
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094fd030 00008148
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#Configure alternate space
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09000010 00000000
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09000014 ff000000
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09000018 81000000
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#Flush PBL data
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09138000 00000000
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091380c0 00000000
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