mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
ba4575626e
Convert this driver over to use driver model. Since all x86 platforms use it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent code and remove the old x86 spi_init() function. Note that this does not make full use of the new PCI uclass as yet. We still scan the bus looking for the device. It should move to finding its details in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
92 lines
2.1 KiB
C
92 lines
2.1 KiB
C
/*
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* (C) Copyright 2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <spi.h>
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#include <asm/errno.h>
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#include <asm/mtrr.h>
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#include <asm/sections.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Get the top of usable RAM */
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__weak ulong board_get_usable_ram_top(ulong total_size)
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{
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return gd->ram_size;
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}
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int calculate_relocation_address(void)
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{
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const ulong uboot_size = (uintptr_t)&__bss_end -
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(uintptr_t)&__text_start;
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ulong total_size;
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ulong dest_addr;
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ulong fdt_size = 0;
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#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
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if (gd->fdt_blob)
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fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
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#endif
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total_size = ALIGN(uboot_size, 1 << 12) + CONFIG_SYS_MALLOC_LEN +
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CONFIG_SYS_STACK_SIZE + fdt_size;
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dest_addr = board_get_usable_ram_top(total_size);
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/*
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* NOTE: All destination address are rounded down to 16-byte
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* boundary to satisfy various worst-case alignment
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* requirements
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*/
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dest_addr &= ~15;
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#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
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/*
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* If the device tree is sitting immediate above our image then we
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* must relocate it. If it is embedded in the data section, then it
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* will be relocated with other data.
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*/
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if (gd->fdt_blob) {
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dest_addr -= fdt_size;
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gd->new_fdt = (void *)dest_addr;
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dest_addr &= ~15;
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}
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#endif
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/* U-Boot is below the FDT */
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dest_addr -= uboot_size;
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dest_addr &= ~((1 << 12) - 1);
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gd->relocaddr = dest_addr;
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gd->reloc_off = dest_addr - (uintptr_t)&__text_start;
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/* Stack is at the bottom, so it can grow down */
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gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN;
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return 0;
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}
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int init_cache_f_r(void)
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{
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#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP)
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int ret;
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ret = mtrr_commit(false);
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/* If MTRR MSR is not implemented by the processor, just ignore it */
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if (ret && ret != -ENOSYS)
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return ret;
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#endif
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/* Initialise the CPU cache(s) */
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return init_cache();
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}
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bd_t bd_data;
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int init_bd_struct_r(void)
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{
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gd->bd = &bd_data;
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memset(gd->bd, 0, sizeof(bd_t));
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return 0;
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}
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