mirror of
https://github.com/brain-hackers/u-boot-brain
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98f705c9ce
There was for long time no activity in the 4xx area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 4xx, so remove it. Signed-off-by: Heiko Schocher <hs@denx.de>
100 lines
2.3 KiB
C
100 lines
2.3 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#ifdef CONFIG_MPC85xx
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#include <asm/config_mpc85xx.h>
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#endif
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#ifdef CONFIG_MPC86xx
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#include <asm/config_mpc86xx.h>
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#endif
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#ifdef CONFIG_MPC83xx
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#endif
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#ifndef HWCONFIG_BUFFER_SIZE
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#define HWCONFIG_BUFFER_SIZE 256
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#endif
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/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
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#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
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# ifndef CONFIG_HARD_SPI
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# define CONFIG_HARD_SPI
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# endif
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#endif
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#define CONFIG_LMB
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#define CONFIG_SYS_BOOT_RAMDISK_HIGH
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#define CONFIG_SYS_BOOT_GET_CMDLINE
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#define CONFIG_SYS_BOOT_GET_KBD
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#ifndef CONFIG_MAX_MEM_MAPPED
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#if defined(CONFIG_E500) || \
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defined(CONFIG_MPC86xx) || \
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defined(CONFIG_E300)
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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#else
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#define CONFIG_MAX_MEM_MAPPED (256 << 20)
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#endif
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#endif
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/* Check if boards need to enable FSL DMA engine for SDRAM init */
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#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
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#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
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((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
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!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
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#define CONFIG_FSL_DMA
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#endif
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#endif
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/*
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* Provide a default boot page translation virtual address that lines up with
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* Freescale's default e500 reset page.
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*/
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#if (defined(CONFIG_E500) && defined(CONFIG_MP))
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#ifndef CONFIG_BPTR_VIRT_ADDR
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#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
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#endif
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#endif
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/* Since so many PPC SOCs have a semi-common LBC, define this here */
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
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defined(CONFIG_MPC83xx)
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#if !defined(CONFIG_FSL_IFC)
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#define CONFIG_FSL_LBC
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#endif
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#endif
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/* The TSEC driver uses the PHYLIB infrastructure */
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#ifndef CONFIG_PHYLIB
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_PHYLIB
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#include <config_phylib_all_drivers.h>
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#endif /* TSEC_ENET */
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#endif /* !CONFIG_PHYLIB */
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/* The FMAN driver uses the PHYLIB infrastructure */
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#if defined(CONFIG_FMAN_ENET)
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#define CONFIG_PHYLIB
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#endif
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/* All PPC boards must swap IDE bytes */
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#define CONFIG_IDE_SWAP_IO
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#if defined(CONFIG_DM_SERIAL)
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/*
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* TODO: Convert this to a clock driver exists that can give us the UART
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* clock here.
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*/
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#endif
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#endif /* _ASM_CONFIG_H_ */
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