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https://github.com/brain-hackers/u-boot-brain
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828d9af5ec
Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
71 lines
1.4 KiB
C
71 lines
1.4 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/arch/device.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_PREF_BUS,
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CONFIG_PCI_PREF_PHYS,
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CONFIG_PCI_PREF_SIZE,
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PCI_REGION_PREFETCH);
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pci_set_region(hose->regions + 3,
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0,
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0,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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}
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int board_pci_post_scan(struct pci_controller *hose)
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{
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return 0;
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}
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int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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/*
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* TODO:
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*
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* For some unknown reason, the PCI enumeration process hangs
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* when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1).
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*
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* For now we just skip these two devices, and this needs to
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* be revisited later.
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*/
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if (dev == QUARK_HOST_BRIDGE ||
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dev == QUARK_PCIE0 || dev == QUARK_PCIE1) {
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return 1;
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}
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return 0;
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}
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