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https://github.com/brain-hackers/u-boot-brain
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![Robert P. J. Day](/assets/img/avatar_default.png)
Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
355 lines
15 KiB
Plaintext
355 lines
15 KiB
Plaintext
#
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# Copyright 2014-2015 Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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Freescale LayerScape with Chassis Generation 3
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This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
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for example LS2080A.
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DDR Layout
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============
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Entire DDR region splits into two regions.
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- Region 1 is at address 0x8000_0000 to 0xffff_ffff.
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- Region 2 is at 0x80_8000_0000 to the top of total memory,
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for example 16GB, 0x83_ffff_ffff.
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All DDR memory is marked as cache-enabled.
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When MC and Debug server is enabled, they carve 512MB away from the high
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end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
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with MC and Debug server enabled. Linux only sees 15.5GB.
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The reserved 512MB layout looks like
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+---------------+ <-- top/end of memory
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| 256MB | debug server
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+---------------+
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| 256MB | MC
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+---------------+
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| ... |
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MC requires the memory to be aligned with 512MB, so even debug server is
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not enabled, 512MB is reserved, not 256MB.
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Flash Layout
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============
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(1) A typical layout of various images (including Linux and other firmware images)
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is shown below considering a 32MB NOR flash device present on most
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pre-silicon platforms (simulator and emulator):
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-------------------------
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| FIT Image |
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| (linux + DTB + RFS) |
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------------------------- ----> 0x0120_0000
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| Debug Server FW |
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------------------------- ----> 0x00C0_0000
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| AIOP FW |
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------------------------- ----> 0x0070_0000
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| MC FW |
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------------------------- ----> 0x006C_0000
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| MC DPL Blob |
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------------------------- ----> 0x0020_0000
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| BootLoader + Env|
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------------------------- ----> 0x0000_1000
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| PBI |
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------------------------- ----> 0x0000_0080
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| RCW |
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------------------------- ----> 0x0000_0000
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32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
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(2) A typical layout of various images (including Linux and other firmware images)
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is shown below considering a 128MB NOR flash device present on QDS and RDB
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boards:
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----------------------------------------- ----> 0x5_8800_0000 ---
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| .. Unused .. (7M) | |
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----------------------------------------- ----> 0x5_8790_0000 |
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| FIT Image (linux + DTB + RFS) (40M) | |
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----------------------------------------- ----> 0x5_8510_0000 |
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| PHY firmware (2M) | |
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----------------------------------------- ----> 0x5_84F0_0000 | 64K
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| Debug Server FW (2M) | | Alt
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----------------------------------------- ----> 0x5_84D0_0000 | Bank
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| AIOP FW (4M) | |
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----------------------------------------- ----> 0x5_8490_0000 (vbank4)
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| MC DPC Blob (1M) | |
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----------------------------------------- ----> 0x5_8480_0000 |
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| MC DPL Blob (1M) | |
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----------------------------------------- ----> 0x5_8470_0000 |
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| MC FW (4M) | |
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----------------------------------------- ----> 0x5_8430_0000 |
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| BootLoader Environment (1M) | |
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----------------------------------------- ----> 0x5_8420_0000 |
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| BootLoader (1M) | |
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----------------------------------------- ----> 0x5_8410_0000 |
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| RCW and PBI (1M) | |
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----------------------------------------- ----> 0x5_8400_0000 ---
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| .. Unused .. (7M) | |
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----------------------------------------- ----> 0x5_8390_0000 |
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| FIT Image (linux + DTB + RFS) (40M) | |
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----------------------------------------- ----> 0x5_8110_0000 |
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| PHY firmware (2M) | |
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----------------------------------------- ----> 0x5_80F0_0000 | 64K
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| Debug Server FW (2M) | | Bank
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----------------------------------------- ----> 0x5_80D0_0000 |
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| AIOP FW (4M) | |
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----------------------------------------- ----> 0x5_8090_0000 (vbank0)
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| MC DPC Blob (1M) | |
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----------------------------------------- ----> 0x5_8080_0000 |
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| MC DPL Blob (1M) | |
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----------------------------------------- ----> 0x5_8070_0000 |
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| MC FW (4M) | |
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----------------------------------------- ----> 0x5_8030_0000 |
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| BootLoader Environment (1M) | |
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----------------------------------------- ----> 0x5_8020_0000 |
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| BootLoader (1M) | |
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----------------------------------------- ----> 0x5_8010_0000 |
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| RCW and PBI (1M) | |
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----------------------------------------- ----> 0x5_8000_0000 ---
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128-MB NOR flash layout for QDS and RDB boards
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Environment Variables
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=====================
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mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
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the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
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mcmemsize: MC DRAM block size. If this variable is not defined, the value
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CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
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mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
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from the location where it is stored(NOR, NAND, SD, SATA, USB)during
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u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
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will be null and MC will not be booted and DPL will not be applied
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during U-boot booting.However the MC, DPC and DPL can be applied from
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console independently.
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The variable needs to be set from the console once and then on
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rebooting the parameters set in the variable will automatically be
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executed. The commmand is demostrated taking an example of mc boot
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using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
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cp.b 0xa0000000 0x580300000 $filesize
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cp.b 0x80000000 0x580800000 $filesize
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cp.b 0x90000000 0x580700000 $filesize
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setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
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If only linux is to be booted then the mcinitcmd environment should be set as
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setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
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Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
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MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000
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and 0x580700000 are addresses in NOR where these are copied. It is to be
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noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
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can be replaced with the addresses of DDR to
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which these will be copied in case of these binaries being stored in other
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devices like SATA, USB, NAND, SD etc.
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Booting from NAND
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-------------------
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Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
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The difference between NAND boot RCW image and NOR boot image is the PBI
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command sequence. Below is one example for PBI commands for QDS which uses
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NAND device with 2KB/page, block size 128KB.
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1) CCSR 4-byte write to 0x00e00404, data=0x00000000
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2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
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The above two commands set bootloc register to 0x00000000_1800a000 where
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the u-boot code will be running in OCRAM.
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3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
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BLOCK_SIZE=0x00014000
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This command copies u-boot image from NAND device into OCRAM. The values need
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to adjust accordingly.
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SRC should match the cfg_rcw_src, the reset config pins. It depends
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on the NAND device. See reference manual for cfg_rcw_src.
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SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
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the example above, 128KB. For easy maintenance, we put it at
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the beginning of next block from RCW.
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DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
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BLOCK_SIZE is the size to be copied by PBI.
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RCW image should be written to the beginning of NAND device. Example of using
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u-boot command
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nand write <rcw image in memory> 0 <size of rcw image>
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To form the NAND image, build u-boot with NAND config, for example,
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ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
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The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
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nand write <u-boot image in memory> 200000 <size of u-boot image>
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With these two images in NAND device, the board can boot from NAND.
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Another example for RDB boards,
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1) CCSR 4-byte write to 0x00e00404, data=0x00000000
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2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
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3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
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BLOCK_SIZE=0x00014000
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nand write <rcw image in memory> 0 <size of rcw image>
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nand write <u-boot image in memory> 80000 <size of u-boot image>
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Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
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to match board NAND device with 4KB/page, block size 512KB.
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MMU Translation Tables
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======================
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(1) Early MMU Tables:
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Level 0 Level 1 Level 2
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------------------ ------------------ ------------------
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| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
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------------------ ------------------ ------------------
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| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
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------------------ | ------------------ ------------------
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| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
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------------------ | ------------------ ------------------
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| | 0x00_c000_0000 | | 0x00_0060_0000 |
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| ------------------ ------------------
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| | 0x01_0000_0000 | | 0x00_0080_0000 |
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| ------------------ ------------------
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| ... ...
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| ------------------
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| | 0x05_8000_0000 | --|
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| ------------------ |
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| | 0x05_c000_0000 | |
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| ------------------ |
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| ... |
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| ------------------ | ------------------
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|--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 |
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------------------ ------------------
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| 0x80_4000_0000 | | 0x00_3020_0000 |
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------------------ ------------------
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| 0x80_8000_0000 | | 0x00_3040_0000 |
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------------------ ------------------
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| 0x80_c000_0000 | | 0x00_3060_0000 |
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------------------ ------------------
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| 0x81_0000_0000 | | 0x00_3080_0000 |
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------------------ ------------------
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... ...
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(2) Final MMU Tables:
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Level 0 Level 1 Level 2
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------------------ ------------------ ------------------
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| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
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------------------ ------------------ ------------------
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| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
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------------------ | ------------------ ------------------
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| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
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------------------ | ------------------ ------------------
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| | 0x00_c000_0000 | | 0x00_0060_0000 |
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| ------------------ ------------------
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| | 0x01_0000_0000 | | 0x00_0080_0000 |
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| ------------------ ------------------
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| ... ...
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| ------------------
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| | 0x08_0000_0000 | --|
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| ------------------ |
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| | 0x08_4000_0000 | |
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| ------------------ |
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| ... |
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| ------------------ | ------------------
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|--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 |
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------------------ ------------------
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| 0x80_4000_0000 | | 0x08_0020_0000 |
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------------------ ------------------
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| 0x80_8000_0000 | | 0x08_0040_0000 |
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------------------ ------------------
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| 0x80_c000_0000 | | 0x08_0060_0000 |
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------------------ ------------------
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| 0x81_0000_0000 | | 0x08_0080_0000 |
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------------------ ------------------
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... ...
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DPAA2 commands to manage Management Complex (MC)
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------------------------------------------------
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DPAA2 commands has been introduced to manage Management Complex
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(MC). These commands are used to start mc, aiop and apply DPL
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from u-boot command prompt.
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Please note Management complex Firmware(MC), DPL and DPC are no
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more deployed during u-boot boot-sequence.
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Commands:
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a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
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b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
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c) fsl_mc start aiop <FW_addr> - Start AIOP
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How to use commands :-
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1. Command sequence for u-boot ethernet:
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a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
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b) DPMAC net-devices are now available for use
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Example-
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Assumption: MC firmware, DPL and DPC dtb is already programmed
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on NOR flash.
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=> fsl_mc start mc 580300000 580800000
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=> setenv ethact DPMAC1@xgmii
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=> ping $serverip
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2. Command sequence for Linux boot:
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a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
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b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
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c) No DPMAC net-devices are available for use in u-boot
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d) boot Linux
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Example-
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Assumption: MC firmware, DPL and DPC dtb is already programmed
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on NOR flash.
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=> fsl_mc start mc 580300000 580800000
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=> setenv ethact DPMAC1@xgmii
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=> tftp a0000000 kernel.itb
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=> fsl_mc apply dpl 580700000
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=> bootm a0000000
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3. Command sequence for AIOP boot:
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a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
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b) fsl_mc start aiop <FW_addr> - Start AIOP
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c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
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d) No DPMAC net-devices are availabe for use in u-boot
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Please note actual AIOP start will happen during DPL parsing of
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Management complex
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Example-
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Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
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programmed on NOR flash.
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=> fsl_mc start mc 580300000 580800000
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=> fsl_mc start aiop 0x580900000
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=> setenv ethact DPMAC1@xgmii
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=> fsl_mc apply dpl 580700000
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Errata A009635
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---------------
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If the core runs at higher than x3 speed of the platform, there is
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possiblity about sev instruction to getting missed by other cores.
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This is because of SoC Run Control block may not able to sample
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the EVENTI(Sev) signals.
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Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
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wake up A57 cores
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Errata workaround uses Env variable "a009635_interval_val". It uses decimal
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value.
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- Default value of env variable is platform clock (MHz)
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- User can modify default value by updating the env variable
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setenv a009635_interval_val 600; saveenv;
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It configure platform clock as 600 MHz
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- Env variable as 0 signifies no workaround
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