mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
7682a99826
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
147 lines
4.1 KiB
ArmAsm
147 lines
4.1 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the Samsung SMDK2410 by
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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/* some parameters for the board */
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/*
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*
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* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
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*
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* Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
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*
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*/
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#define BWSCON 0x48000000
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/* BWSCON */
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#define DW8 (0x0)
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#define DW16 (0x1)
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#define DW32 (0x2)
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#define WAIT (0x1<<2)
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#define UBLB (0x1<<3)
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#define B1_BWSCON (DW32)
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#define B2_BWSCON (DW16)
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#define B3_BWSCON (DW16 + WAIT + UBLB)
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#define B4_BWSCON (DW16)
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#define B5_BWSCON (DW16)
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#define B6_BWSCON (DW32)
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#define B7_BWSCON (DW32)
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/* BANK0CON */
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#define B0_Tacs 0x0 /* 0clk */
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#define B0_Tcos 0x0 /* 0clk */
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#define B0_Tacc 0x7 /* 14clk */
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#define B0_Tcoh 0x0 /* 0clk */
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#define B0_Tah 0x0 /* 0clk */
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#define B0_Tacp 0x0
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#define B0_PMC 0x0 /* normal */
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/* BANK1CON */
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#define B1_Tacs 0x0 /* 0clk */
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#define B1_Tcos 0x0 /* 0clk */
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#define B1_Tacc 0x7 /* 14clk */
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#define B1_Tcoh 0x0 /* 0clk */
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#define B1_Tah 0x0 /* 0clk */
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#define B1_Tacp 0x0
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#define B1_PMC 0x0
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#define B2_Tacs 0x0
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#define B2_Tcos 0x0
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#define B2_Tacc 0x7
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#define B2_Tcoh 0x0
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#define B2_Tah 0x0
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#define B2_Tacp 0x0
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#define B2_PMC 0x0
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#define B3_Tacs 0x0 /* 0clk */
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#define B3_Tcos 0x3 /* 4clk */
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#define B3_Tacc 0x7 /* 14clk */
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#define B3_Tcoh 0x1 /* 1clk */
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#define B3_Tah 0x0 /* 0clk */
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#define B3_Tacp 0x3 /* 6clk */
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#define B3_PMC 0x0 /* normal */
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#define B4_Tacs 0x0 /* 0clk */
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#define B4_Tcos 0x0 /* 0clk */
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#define B4_Tacc 0x7 /* 14clk */
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#define B4_Tcoh 0x0 /* 0clk */
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#define B4_Tah 0x0 /* 0clk */
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#define B4_Tacp 0x0
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#define B4_PMC 0x0 /* normal */
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#define B5_Tacs 0x0 /* 0clk */
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#define B5_Tcos 0x0 /* 0clk */
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#define B5_Tacc 0x7 /* 14clk */
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#define B5_Tcoh 0x0 /* 0clk */
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#define B5_Tah 0x0 /* 0clk */
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#define B5_Tacp 0x0
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#define B5_PMC 0x0 /* normal */
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#define B6_MT 0x3 /* SDRAM */
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#define B6_Trcd 0x1
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#define B6_SCAN 0x1 /* 9bit */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd 0x1 /* 3clk */
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#define B7_SCAN 0x1 /* 9bit */
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/* REFRESH parameter */
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#define REFEN 0x1 /* Refresh enable */
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
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#define Trp 0x0 /* 2clk */
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#define Trc 0x3 /* 7clk */
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#define Tchr 0x2 /* 3clk */
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#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
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/**************************************/
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.globl lowlevel_init
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lowlevel_init:
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads SMRDATA out of FLASH rather than memory ! */
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ldr r0, =SMRDATA
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ldr r1, =CONFIG_SYS_TEXT_BASE
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sub r0, r0, r1
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ldr r1, =BWSCON /* Bus Width Status Controller */
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add r2, r0, #13*4
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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bne 0b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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/* the literal pools origin */
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SMRDATA:
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.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
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.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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.word 0x32
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.word 0x30
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.word 0x30
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